# AMD/Intel CPU Yield/Failure Rate

This question is based on another question submitted here: Is it possible to make illegal clones of an Intel Core i7?

More specifically, it's based around this quote:

I've been led to believe it's something like a 60% yield (i.e. they produce 100 processors they only get 60 that actually work) and the rest have to be discarded.

I'm incredibly curious now. What's the usual yield like for AMD and Intel CPUs? Is this actually documented anywhere or is it something not often spoken about by either company? Are there any articles or external information AMD and Intel have released on the failure rate of the CPUs they produce?

Also, is there any documentation on exactly why AMD or Intel CPUs might fail during production? I understand today's CPUs are immensely complex beasts, but, given the environment they're manufactured in, is a 40% failure rate really that acceptable (assuming the poster's claim of a 40% failure rate is even accurate)?

• My father used to observe that their best yields were in the summer holiday, when engineering students filled in for the regular plant workers :) – MSalters Aug 23 '13 at 15:09
• While there are some really fascinating answers here, the whole page reads like a discussion rather than a Q & A about a specific problem you are currently facing, with your work so far described. – Martin Aug 23 '13 at 16:05
• Yes, yields can be low (even just 30%) due to process variation and other factors, see my survey paper which references multiple papers discussing this. – user984260 Dec 10 '15 at 13:12

Yield rates are definitely a commercial secret; they will likely vary from batch to batch with normal manufacturing variation and attempts to tune the process to increase yield.

Yield is inversely proportional to die size. The i7 die size for "Lynnfield" is 296 mm², according to wikipedia, which is pretty big.

Yield is also traditionally low on newer manufacturing processes. Intel are always on the cutting edge, as part of their "high performance / high cost" market strategy.

Spot failures are usually due to tiny imperfections in the silicon substrate crystal. There are also the usual alignment and patterning issues which may cause whole wafers to fail. Generally the whole thing is a very nasty process control problem; dopants and chemical reactions have to be applied completely evenly, again and again in each of the layers. A single tiny bubble will cause a failure.

• Big is relative though. nVidia's current flagship chip the GK110 is 551mm^2 in size; and the Tukwilla Itanium was 699 mm^2. – Dan Neely Aug 23 '13 at 18:56
• Not all defects are fatal to a die. Most large memory arrays (caches often use half or more of the area) have redundancy to compensate for defects. Also in a multicore chip, a 6-core implementation can be sold as a 4-core chip if one or two cores are defective. Furthermore, some process variation can be managed by product binning; not all chips have to be equally well-formed. – Paul A. Clayton Aug 23 '13 at 21:22
• It might be worthwhile to note Intel's tick-tock strategy which balances risk by having the initial use a new process produce chips with an established microarchitecture. (Also, previously Intel could use a noticeable amount of older production capacity for chipsets.) – Paul A. Clayton Aug 23 '13 at 21:44
• @DanNeely the light sensing area of a sensor for a 35mm full-frame camera is 864mm<sup>2</sup>, and that doesn't include the peripheral circuitry like A/D converters. I'm guessing they don't use bleeding edge processes so they can get better yields. – Mark Ransom Jan 22 '18 at 17:37

There are various methods of modelling yield that are appropriate during different process steps. The most conservative is the exponential rule and therefore the safest to model with (you will produce more die per wafer than predicted).

$Y = Ke^{DA}$ Where D = Defect density, A = Area, K is a scale factor and Y = Yield.

This equation allows you to predict from yield at one size to yield at another size.

$\dfrac{Y_1}{Y_2} = e^{D(A_1 - A_2)}$

Running some numbers with the following assumptions:

- 300 mm wafer,
- 100 um scribe,
- 5 mm wafer edge bead,
- and 17.2 mm X 17.2 mm die size.


There will be 188 GDPW (Gross die per wafer - from some software I have). If we assume the 60% yield from above, that is 113 DPW. With a high estimate of $3000 per wafer that is$26 per die after yield. Given how much Intel sells a packaged part for you can see that 60%, while crappy, is not the end of the world for them, they should be able to maintain their 10X margins ...

Looking at the lithography size and the size of the die, 60% also seems reasonable.

• The profit margin must also take into account design effort. I also suspect that wafer cost for leading edge process technology might be greater than \$3000 (with fabs becoming increasingly expensive and an increasing number of steps being involved in production). – Paul A. Clayton Aug 23 '13 at 21:16

There is no one single number which represents yield of a manufacturer. The yields vary between technologies, fabs and dies. It also varies with time.

In general, when the technology is just released and is not mature, the yields will be low. Process engineers work very hard in order to enhance the manufacturing process and obtain high yields. The reasons for which the die can fail include (but not restricted to):

• Imperfections present on raw initial silicon wafer (for example: too contaminated silicon crystal)
• Imperfections added in the pre-production wafer's handling (for example: physical defects produced during native oxide etching)
• Failures during active devices patterning (for example: insufficient/excessive doping, defects in insulation layers, improper alignment)
• Failures during metals routing (for example: short/open circuits, disconnected vias)

There are two general factors which can lower the yield: overusing the thermal budget and failures in chemical reactions. The thermal budget is the amount of heat the die can be exposed to without being damaged (usually determined experimentally). I know nothing about chemical reactions, but I know that even slightest error in chemicals constitution can ruin not just a single die, but the entire batch.

It is very hard to obtain high yields in sub-micron processes, therefore Intel came with the "Copy-Exactly" strategy: all the controllable factors are the same across all its fabs. This ensures that once the primary fab gets to high yields, the secondary fabs will get there in the shortest possible time.

The yield numbers are trade secrets. However, it is widely known fact that it becomes more and more difficult to get high yields which more advanced technologies. The number of 60% yield seems too low to me - this might be an initial yield when the technology is not mature enough, but this is too low for large scale manufacturing.

• You mis-spelled Copy Exactly!. It even has an exclamation point when abbreviated as "CE!". – The Photon Aug 23 '13 at 18:05
• There is also not necessarily a clear dividing line between process variation and defects. If a critical path has excessively slow transistors, then that portion will not meet the timing requirements for a part that can be sold profitably (e.g., not taking revenue away from other parts, not causing confusion that weakens brand perception, not covering marketing/tracking costs for an SKU). – Paul A. Clayton Aug 23 '13 at 21:30