How to choose flip flop type for implementation in moore or mealy state diagram? I can't understand this thing. Could someone help me? There are t-type, d-type, s-r type, j-k type. How to choose one of best flip flop?

  • \$\begingroup\$ What's wrong with using a D flip-flop? \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 25 '13 at 4:54
  • \$\begingroup\$ He doesn't know. That's why he's posting this question. \$\endgroup\$ – Nick Alexeev Aug 25 '13 at 5:32
  • \$\begingroup\$ You can configure a JK-FF (the most 'complex' of them) to act as any other FF (T, D, SR). \$\endgroup\$ – jippie Aug 25 '13 at 7:11
  • \$\begingroup\$ What exactly do you want your FF's to do? Describe this, and compare it to the characteristics of the FF's you mention. \$\endgroup\$ – Wouter van Ooijen Aug 25 '13 at 7:29
  • \$\begingroup\$ Moore machines change outputs synchronously and Mealy machines are asynchronous. \$\endgroup\$ – JIm Dearden Aug 25 '13 at 8:21

The choice is purely arbitrary. Some flip-flop types can reduce the complexity of your next-state logic. However it is really hard to say which one will be best because you would need to check every flip-flop type with every encoding you could possibly use.

D flip-flops are easy to use because its excitation is exactly the same as the next state.

If you plan to use CPLDs or FPGAs to implement your machine use D flip-flops as they will have a D flip-flop built in. their

  • \$\begingroup\$ +1 In CMOS logic flip-flops are usually built with transmission gates and the D type is the most natural (fewest transistors) type. The J-K, T, and similar relics of TTL are best forgotten. \$\endgroup\$ – Joe Hass Aug 25 '13 at 13:43
  • \$\begingroup\$ @JoeHass: The T flop is very useful in CPLD designs, since in many cases the number of product terms to describe cases where a latch should change is much smaller than the number required for it to remain high or to remain low. \$\endgroup\$ – supercat Aug 31 '13 at 23:02

Many CPLD types allow flip flops to be independently configured for D or T operation; the T option will cause the output of the flop to be XOR'ed into the input. Many pieces of placement software will by default attempt logic reduction using both types of flip flop and use whichever kind requires the fewest product terms. In general, D flops are good when outputs are supposed to be forced to one particular state except when a combination of conditions applies, while T flops are good if outputs are supposed to stay put except when a combination of conditions applies. As an example of a place where a T flop wins, consider an output Q0 which is supposed to latch D0 when A0-A15 are all set, and remain put otherwise. Using a T flop would require two product terms:

Toggle output if either:
  A0-A15 are set, Q0 is clear, and D0 is set, or
  A0-A15 are set, Q0 is set, and D0 is clear

By contrast, using a D flop would require 17 product terms:

Set output if either:
  A0-A15 are set and D0 is set, or
  Q0 is set and A0 is clear, or
  Q0 is set and A1 is clear, or
  Q0 is set and A15 is clear

If one had an output Q1 which was supposed to be clear unless A0-A15 along with D1 were all set, a D flop would be one product term:

Set output if:
  A0-A15 are set and D1 are set

Using a T flop would require 18 product terms:

Toggle output if:
  Q1 is clear, A0-15 are set, D1 is set
  Q1 is set and A0 is clear
  Q1 is set and A1 is clear
  Q1 is set and A15 is clear
  Q1 is set and D1 is clear

Note that a JK flip flop may be emulated pretty well using a T flop, using the formula T=(!Q & J) | (Q & !K). The primary limitation with such emulation in a CPLD is that K is inverted relative to J; in a CPLD it's possible that both J and K would be representable with few product terms, while both !J and !K are require many, or vice versa.

The differences between flop types are not nearly as great in an FPGAs as in CPLDs, since any type of flop may be emulated in terms of any other with the addition of a small amount of simple logic (e.g. either a D or T flop may be implemented in terms of the other by adding a single XOR gate), and FPGAs have a large number of simple logic circuits (as opposed to CPLDs which have a small number of complex circuits). Consequently, having to use a logic element to compute an "intermediate value" represents a much smaller "loss" in an FPGA design than in a CPLD design.

One parting note: regardless of the states of their outputs, the states of a D flip flop will be well defined if certain input conditions apply on the next clip (the D flop output will be defined if its input is; the JK flop will be defined if J and K are have defined high-and-low or low-and-high values). Even if the outputs somehow latched a half-high value, it would be forced to a clean high or low on the next cycle. A T latch may, at least in theory, not have such a property. If it somehow gets latched into an indeterminate half-high state, the effects of trying to compute the T input may yield indeterminate results and the latch could remain in an indeterminate half-high state.


Personally I would standardize on a J-K flip flop rather than use a range of types because the behavior of the JK flip-flop is completely predictable under all conditions. However D types could equally be used. I would avoid SR, T etc. as they can all be derived (as Jippie points out) from the JK type.

Have a look at http://www.allaboutcircuits.com/vol_4/chpt_11/5.html as an example of finite state machine design using flip flops.


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