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Just a theoretical question more than anything. Does the clock signal have to have the same width between peeks and troughs?

A normal clock signal with data (below):

Normal Clock

A random clock signal with data (the data is still in sync with the clock) (below):

Random Clock

Would the chip (any chip in general, but as an example, a serial in parallel out shift register) still behave normally with a more random clock? If not, why not?

Again, not that I am planning to do this, but theoretically is there any reason that I could not use a standard ouput pin on the Raspberry Pi/Arduino as the clock and another pin as the data?

Example pseudo code:

fakeClockPin = 1;
dataPin = 2;

setPin(dataPin, HIGH);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms

setPin(dataPin, LOW);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms

setPin(dataPin, HIGH);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms

setPin(dataPin, LOW);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms
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  • \$\begingroup\$ Not all clocks are symmetrical. Certain old microprocessors needed a 66% duty cycle (if I remember right) clock. \$\endgroup\$
    – HL-SDK
    Aug 28, 2013 at 18:25
  • 1
    \$\begingroup\$ The technique described by your pseudo-code is called bit banging, and it's a perfectly legitimate thing to do. \$\endgroup\$
    – Phil Frost
    Aug 11, 2014 at 16:19

3 Answers 3

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Your clock signal is edge-triggering, in your examples on the positive edge. You can tell because the data has to be stable a short time before the clock edge (setup time), and if the clock would latch on the falling edge it would coincide with your data changing.

Except for the setup time there are few constraints: the clock may stay high as long as it wants. You will have to have a minimum low time however, before the next rising edge.

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A chip will behave normally as long as you operate it within the 'normal operation parameters' as specified in the datasheet. Most chips have only requirements about the minimum time between clock edges, and the setup time (data stable to active clock edge). Neither are violated by stretching the clock.

In practice, a software-generated clock signal will always have large variations in timing. The important point is that you don't do things too fast for the external chip. But the timing of a typical shift register is expressed in 10's of ns, which is a few orders faster than the 1 ms you observe.

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A simple chip with a "clock pin" doesn't care when the clock edge arrives, only that it does. Even, isochronous pulses are more for the benefit of software or more complex hardware, e.g. PLL-based devices.

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