# Theoretical Clock Question

Just a theoretical question more than anything. Does the clock signal have to have the same width between peeks and troughs?

A normal clock signal with data (below):

A random clock signal with data (the data is still in sync with the clock) (below):

Would the chip (any chip in general, but as an example, a serial in parallel out shift register) still behave normally with a more random clock? If not, why not?

Again, not that I am planning to do this, but theoretically is there any reason that I could not use a standard ouput pin on the Raspberry Pi/Arduino as the clock and another pin as the data?

Example pseudo code:

fakeClockPin = 1;
dataPin = 2;

setPin(dataPin, HIGH);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms

setPin(dataPin, LOW);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms

setPin(dataPin, HIGH);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms

setPin(dataPin, LOW);
setPin(fakeClockPin, HIGH);
sleep(1); //1ms
setPin(fakeClockPin, LOW);
sleep(1); //1ms

• Not all clocks are symmetrical. Certain old microprocessors needed a 66% duty cycle (if I remember right) clock. Aug 28, 2013 at 18:25
• The technique described by your pseudo-code is called bit banging, and it's a perfectly legitimate thing to do. Aug 11, 2014 at 16:19