I'm working on a Microblaze-based system. I'm using FSL to shuttle data directly from an AC'97 controller core to my custom DSP core. The FSL buses are clocked at the 125MHz system clock. The DSP components have been designed with a 48kHz clock in mind (the codec sampling rate).
How do I go about clocking the samples through the DSP components at 48kHz?
FSL bus is essentially a FIFO, that signals when data is available for the slave to read. Through some experimentation, I'm seeing samples arrive at approximately 48 kHz (I was using a timer interrupt in the uBlaze to monitor this, hence the "approximately"). Is there any way I can generate a sane "clock" from this fact, and also allow XST to understand the timing requirements of what I'm doing?