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The following circuit modulates the SIG wave with a 1kHz CLK signal and produces the OUT resulting wave.circuit

I have read that the superimposed wave has an amplitude of the sum of the original waves. If two waves are ASIN(wt) and BSIN(wt) then the superimposed wave has an amplitude of A+B.

What I don't understand is why the OUT wave has less amplitude than then the SIG wave, when the SIG and the CLK are in phases!

If we zoom in we can see some detail:

The amplitude of SIG wave is = 2V The amplitude of CLK wave is = 1V

How to calculate the amplitude of the OUT wave?

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Because you seem to be using a simulator in your question, try putting the voltage sources in series with one of the sources at ground then measure at the open end of the other. This should confirm to you that using resistors you get each sinewave attenuated by 6dB.

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  • \$\begingroup\$ I see what is happening. The register divider is just halfing the resulting wave. Thanks. \$\endgroup\$ – Arjob Mukherjee Aug 29 '13 at 9:27
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The issue is you're not adding the two waves, you're taking the midpoint between the instantaneous value of each.

Basically, the resistor divider you have constructed has an output that is a function of the voltages at each end. In this case, since the two values are equal, the voltage divider basically splits the difference between the two values.

If you want to actually sum the inputs, rather then average them, you will need an active circuit (usually implemented using an op-amp).

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  • \$\begingroup\$ So, the voltage divider is dividing (averaging) the resulting voltage! The register divider is dividing the 1+2=3V to 1.5v. \$\endgroup\$ – Arjob Mukherjee Aug 29 '13 at 9:25

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