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Is there a reference or what is the explanation for I²C and SPI being just physical layer protocols in the OSI model (I know that this model is for communication and maybe not exactly for on-board buses) or is the data link layer protocol defined inside them?

How about the CAN protocol?

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    \$\begingroup\$ This question appears to be off-topic because it is not about electronic design. \$\endgroup\$ Aug 29 '13 at 11:04
  • \$\begingroup\$ Hi, i wanted to question it in stackoverflow, but i think folks there will say that it's not a programming question even though SPI & I2C tags are found in both groups. you can see my last question about UART protocol in stackoverflow and the commend and negative points that i got because folks there think the question should be asked in electronics.stackexchange.com and that's why i opened this account Yesterday. \$\endgroup\$
    – Michelle
    Aug 29 '13 at 11:56
  • \$\begingroup\$ here is the link:stackoverflow.com/questions/18459505/… \$\endgroup\$
    – Michelle
    Aug 29 '13 at 11:57
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    \$\begingroup\$ Low level hardware protocols like SPI, IIC, and CAN are relevant to electrical engineering, so I think this is on topic here, even if the specific question is rather theoretical with its answer pointless in a practical sense. \$\endgroup\$ Aug 29 '13 at 14:07
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Both. The OSI stack is so abstract that virtually any protocol used in industry is highly likely to contain practical considerations that effectively implement multiple levels.

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  • \$\begingroup\$ if these protocols have their data link layer definition inside, it means that it's not me who define how the frame is populated (combination of address, data and commands),it's already defined in SPI or I2C that for example, the first 3 bits are address bits, then we have 4 bits of data, then again we have 2 address bits,etc. but nowhere in the net i found this information.could you please explain more? \$\endgroup\$
    – Michelle
    Aug 29 '13 at 14:32
  • \$\begingroup\$ These industry protocols almost always contain definitions of multiple layers, if not explicitly, then implicitly, by their assumption that these bit-formats will be used in a certain way. The real test of whether something like a bit-format is only a data layer would be to show that multiple, isolated protocols use the same Data layer, without modification. This is rarely the case, as each protocol has specific needs hat start to leak into the Data and Physical layers. \$\endgroup\$ Aug 29 '13 at 15:13
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I2C operates in terms of defined transactions, with arbitration and handshaking, so it may reasonably be thought of as a data link layer as well as a physical one, even though it doesn't necessarily fit the OSI pattern terribly well. SPI isn't really a standard so much as a term which is used to describe a wide variety of communications designs. As such, it barely even qualifies as a physical layer protocol.

With both SPI and I2C, one can advance to higher layers if one restricts one's focus to particular styles of chip. For example, there's a common standard for I2C EEPROMs up to 2Kbytes, and another which would be applicable to I2C EEPROMs up to 512Kbytes (though I've not seen devices that big use it). Such standards not only define how to perform transactions on the chip, but also specifies what the chip will do with the data contained therein.

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Nothing so explicit. You can attempt to define certain parts of the I²C protocol to different OSI layers, but how you define them and how someone else defines them would not match (ask five engineers and get seven different answers).

My take on it is that the physical layer is the simplest. I²C requires two open-collector bus lines, tied to VCC with pullup resistors of X value, limited to Y pF of capacitance (where X and Y are calculated based on the desired frequency of the I²C bus). The I²C devices should release the line when idle, and only pull the line low when actively communicating. That's the physical layer.

The data layer is a bit more complex. I²C masters, especially in a multi-master system, should when trying to communicate, check to see if the lines are pulled low, if free, attempt communication, check the line again. If at any time it's unexpectedly low, follow arbitration protocols. I²C slaves (and masters) can also implement clock stretching, controlling communication by preventing clock pulses.

Physical and logical addressing fall under both the data link layer and the network layer, if you include bus expanders/multiplexers/buffers/hot swap ICs. I²C doesn't really have a network topology or IP equivalent, with bus expanders being a non-specification hacky solution manufacturers have come up with.

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  • \$\begingroup\$ so when i buy a microcontroller which has I²C communication interface and i want to attach it to an on-board peripheral which also has I²C interface, via serial wires,i can follow I²c circuitry definition (physical layer), creating two lines with above resistors,then define my frame(address,data,command) with almost complete freedom, then define some sort of logic which does arbitration,handshaking,...(data link layer stuffs). \$\endgroup\$
    – Michelle
    Aug 30 '13 at 7:53
  • \$\begingroup\$ By reading your explanation, it seems to me that i'm asking like: How to define an OSI model for a parallel RLC circuit? does my question look like that? thanks \$\endgroup\$
    – Michelle
    Aug 30 '13 at 7:56
  • \$\begingroup\$ @Michelle no, not complete freedom. i2c devices expect the "frame" to be start, 7 bit address + 1 bit read/write bit, n bytes of data, stop (or restart). \$\endgroup\$
    – Passerby
    Aug 30 '13 at 17:41

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