I am trying to debug LPC1768 using a JTAG debugger and openOCD(version 0.7.0). My os is Win7 .

I'm connetced to the openOCD via telnet(port 4444) commands like halt, flash info, resume etc do work peoperly.

Now when I do

flash erase_sector 0 0 0

I get the follow reply

erased sectors 0 through 0 on flash bank 0 in 5.705326s

then I do

mdw 0 7

and it returns

0x00000000: 10001ffc 1fff0081 ffffffff ffffffff ffffffff ffffffff ffffffff

What are those first two words? Should it not be all ffffffff?

Snapshot CMD


flash write_bank too has no effect on flash.

I then uploaded the same binary using H-JTAG and it got programmed. So that means my chip isn't bricked!

enter image description here

content of my openocd cfg file

interface parport
gdb_port 3333

gdb_memory_map enable
gdb_flash_program enable

source [find board/mcb1700.cfg]

contents of mcb1700.cfg

# Keil MCB1700 PCB with 1768
# Reset init script sets it to 100MHz
set CCLK 100000 

source [find target/lpc1768.cfg] 

interface parport
parport_port 0x378
parport_cable wiggler

global MCB1700_CCLK
set MCB1700_CCLK $CCLK

$_TARGETNAME configure -event reset-start {
    # Start *real slow* as we do not know the
    # state the boot rom left the clock in
    adapter_khz 100

# Set up 100MHz clock to CPU
$_TARGETNAME configure -event reset-init {
    # PLL0CON: Disable PLL
    mww 0x400FC080 0x00000000
    mww 0x400FC08C 0x000000AA
    mww 0x400FC08C 0x00000055

    # CCLK=PLL/4 (=100 MHz)
    mww 0x400FC104 0x00000003
    # CLKSRCSEL: Clock source = internal RC oscillator
    mww 0x400FC10C 0x00000000

    # PLL0CFG: M=50,N=1 -> PLL=400 MHz
    mww 0x400FC084 0x00000031
    mww 0x400FC08C 0x000000AA
    mww 0x400FC08C 0x00000055

    # PLL0CON: Enable PLL
    mww 0x400FC080 0x00000001
    mww 0x400FC08C 0x000000AA
    mww 0x400FC08C 0x00000055

    sleep 50

    # PLL0CON: Connect PLL
    mww 0x400FC080 0x00000003
    mww 0x400FC08C 0x000000AA
    mww 0x400FC08C 0x00000055

    # Dividing CPU clock by 8 should be pretty conservative
    global MCB1700_CCLK
    adapter_khz [expr $MCB1700_CCLK / 8]

    # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
    # "User Flash Mode" where interrupt vectors are _not_ remapped,
    # and reside in flash instead).
    # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
    # Bit Symbol Value Description Reset
    # value
    # 0 MAP Memory map control. 0
    # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
    # 1 User mode. The on-chip Flash memory is mapped to address 0.
    # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
    # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user

    mww 0x400FC040 0x01

contents of lpc1768.cfg

# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
set CHIPNAME lpc1768
set CPUTAPID 0x4ba00477
set CPURAMSIZE 0x8000
set CPUROMSIZE 0x80000

# After reset the chip is clocked by the ~4MHz internal RC oscillator.
# When board-specific code (reset-init handler or device firmware)
# configures another oscillator and/or PLL0, set CCLK to match; if
# you don't, then flash erase and write operations may misbehave.
# (The ROM code doing those updates cares about core clock speed...)
# CCLK is the core clock frequency in KHz
set CCLK 4000

#Include the main configuration file.
source [find target/lpc17xx.cfg];
  • \$\begingroup\$ Try flash erase_sector 0 0 last -< erase the whole first flash bank. \$\endgroup\$ – Vorac Aug 29 '13 at 14:37
  • \$\begingroup\$ I tried that as well. No effect! \$\endgroup\$ – vvy Aug 29 '13 at 14:37
  • \$\begingroup\$ Another idea. Try flashing the chip with program or flash write_image and see if those succeed. If there are problems again, consider hardware erase of the whole chip, if available. The chip might be locked for some reason. \$\endgroup\$ – Vorac Aug 29 '13 at 14:40
  • \$\begingroup\$ If you are having problems with the JTAG hardware (which sounds unlikely), you can try using the ftdi driver in place of the fd2232 \$\endgroup\$ – Vorac Aug 29 '13 at 14:49
  • \$\begingroup\$ @Vorac My JTAG is a LTP based wiggler clone. And I highly suspect its frequency settings. I'm trying to lower the frequency now! \$\endgroup\$ – vvy Aug 29 '13 at 14:51

You forgot:

reset init

Background: The LPC1768 maps a ROM bootloader by default at addess 0x0. The reset init handler in recent OpenOCD version does the remapping to flash memory.

  • \$\begingroup\$ So I should be doing reset init followed by erase followed by flash followed by gdb debugging ? \$\endgroup\$ – vvy Aug 29 '13 at 20:04
  • \$\begingroup\$ I'm getting this[docs.google.com/file/d/0B_OcX1Wr8s5WUzhUY0QwdUpfUjQ/… Error! Also check the mcb1700.cfg file content in update! seems some mww error. but where? \$\endgroup\$ – vvy Aug 29 '13 at 20:09
  • \$\begingroup\$ Make sure the SRST line is connected and use reset_config srst_only separate \$\endgroup\$ – Turbo J Aug 29 '13 at 20:22
  • \$\begingroup\$ Also, looks a bit like your JTAG speed is too high. \$\endgroup\$ – Turbo J Aug 29 '13 at 20:28
  • \$\begingroup\$ The JTAG-Adapter works well with H-JTAG which doesn't provides GDB debug capability. reset_config srst_only seperate gives this(docs.google.com/file/d/0B_OcX1Wr8s5WYVp1UGVVNzA5MTA/…) output. What JTAG speed should I use here? \$\endgroup\$ – vvy Aug 29 '13 at 20:31

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.