I want to design ALU with 2 select lines , 2 inputs ( n bits ) that do the following:

this is a homework and I want to know what to do, writ to me the steps for design it.
the first thing I thought to do is to build a table with S0,S1,C, then I have 8 rows, and the output will be F. its ok? now what should I do?

S0 S1 C  |  operation
0  0  0  |  S = A+B
0  0  1  |  S = A+B+1
0  1  0  |  S = A transfer?
0  1  1  |  S = A+1(inc)
1  0  0  |  S = B`
1  0  1  |  S = B`+1
1  1  0  |  s = A+B`(negate)
1  1  1  |  S = A+B`+1
  • \$\begingroup\$ Have you learned about K-maps yet? Q-M reduction? Espresso? Anything? \$\endgroup\$ Aug 29, 2013 at 15:13
  • \$\begingroup\$ I know K-maps, if its ok. \$\endgroup\$
    – Ofir Attia
    Aug 29, 2013 at 15:15
  • \$\begingroup\$ @IgnacioVazquez-Abrams how is the table? \$\endgroup\$
    – Ofir Attia
    Aug 29, 2013 at 15:38

3 Answers 3


Have you heard of an n-bit multiplexer? Compute all the functions independently in parallel (with combinatorial logic), and pass the outputs through a multiplexer with the output chosen by the select lines. Multiplexers are a convenient tool for "logical superposition" (no idea if that's a real term, I just made it up).

The way to come up with an optimized solution is to first construct a datapath that can efficiently generate and combine all the intermediate values your problem statement identifies. Then do some logic reduction to generate the various control signals to that datapath as a function of your high level control inputs (S1, S0).

  • \$\begingroup\$ This is precisely how I'd do it myself; looks like you have a 3 term adder with a bunch of MUXes. I'm not sure right off the top of my head if you can reduce the b negation into a specialized third term for the adder. \$\endgroup\$
    – akohlsmith
    Aug 29, 2013 at 15:57
  • \$\begingroup\$ if I want to negate a number what should I do? \$\endgroup\$
    – Ofir Attia
    Aug 29, 2013 at 16:30
  • \$\begingroup\$ This is a very inefficient solution, requiring 4 full adders with 3 addends, when a more efficient solution only requires a single full adder with 3 addends. Logical superposition is indeed a nonsense term. \$\endgroup\$ Aug 30, 2013 at 2:21
  • \$\begingroup\$ @trav1s gates are free (in homework anyway) :-)... \$\endgroup\$
    – vicatcu
    Aug 30, 2013 at 2:51
  • \$\begingroup\$ @OfirAttia if you want to negate a number, flip all the bits, then add 1 to it. \$\endgroup\$
    – vicatcu
    Aug 30, 2013 at 2:53

Few observations you can make:

  1. You just need 1 result for set of control input
  2. ALL the operations that ALU need to perform are possible through an Adder block that has 2 n-bit inputs along with 1 carry input.
  3. Range of inputs you need to feed in is (A, B, B`, 0) and (0, 1) for carry inputs. For example for s1s0 = 01 and C=0, you can feed A and 0 as input to adder and set carry to 0. For C=1, you can set carry to 1.

All this translate to is multiplexer at input followed by an adder.

Even if this is just homework, it's good and important design technique to learn identify redundancies in specification and reduce logic.

  • \$\begingroup\$ If I use it as "black box" in the ALU, you can show me how its look like on Circuit LAB? \$\endgroup\$
    – Ofir Attia
    Aug 30, 2013 at 5:22
  • \$\begingroup\$ @OfirAttia, You can write table just like you have in in your question. Instead on operation for, you can write what inputs you need to derive to feed Adder (in1, in2, carry) for each set of control inputs. \$\endgroup\$
    – mj6174
    Aug 30, 2013 at 14:58

These are just ideas to help, no need to vote.

  • S0 always appears to invert B - use an exclusive or gate for this; B goes to one input and S0 to the other.
  • C always adds a one to the intermediate answer so use this to gate something.
  • When S0 is zero, A is always factored into the answer

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