VHDL 2008 allows us to have unconstrained records. That is a record containing unconstrained vectors:

type dummy is record
    sample : unsigned;
    int    : integer;
end record;

when the record is used to define a signal one writes

signal s : dummy(sample(2 downto 0));

This procedure is handy if one wants to use records in port maps of entities with generic widths.

I like to use integers in some places since it is more convenient to write sig <= 4 than sig <= to_unsigned(4, sig'LENGTH). However if I do not constrain the integer, this might lead to to large types (wasted bits).

Is there a way to constrain these, post-definition, as well?


2 Answers 2


I'm not aware of any way to "post-constrain" an integer like that.

However, in my experience, the synthesis tools will take note of the source of the data that you write to any integer down the line (presumably irrespective of whether the integer is in a record or not, but I haven't tried it) and propagate any constraints from that source onto the destination.


I think what you want to do is declare a subtype for signal 'sig':

subtype sig_type is integer range 0 to SOME_GENERIC;
signal sig : sig_type;

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