prevent metavalues for input ports in VHDL simulation

Question

In my VHDL design I have entities with port definitions similar to this:

entity dummy is
  port( cpl : cplxRecord_t )
end entity

type cplxRecord_t is record
   r1 : anotherRecord_t;
   vec: unsigned;
   lin: std_logic;
   ...
end record

in the architecture I use some standard functions for unsigned, e.g. to_integer(cpl.vec). These complain during simulation startup Metavalue detected. Returning .... I would like to eliminate the cause of these warnings. So far my only idea is to assign a default value to that port. However having to define each element feels like a bad solution, making htis a maintenance headache when elements are added to/removed from the record. Is there some way to initialize the port with all '0' (Zero)?

Q: How do I prevent Metavalue detected warnings, caused by unsigned ports being uninitialized U during design loading and processesd by to_integer?

P.S.: I am using modelsim. And this font makes it hard to differntiate between letter o and zero. O0o

Answer 1

I'm pretty sure you have to assign the whole record. In the past I've created initialisation constants for my records which ease this problem.

As a workaround (in Modelsim at least, probably Aldec as well) you can use a small TCL function to start off your simulation. This function can disable those warnings, run for 1 ps, then re-enable the warnings and run the rest of the simulation.