I'll preface this with the caveat that I'm not that up to date on the interior workings of recent FPGA architectures. So this answer may not be appropos. depending upon whether the FPGA tools support the design flow I will discuss.
It's probably true the total volume of raw gates shipped into the market are probably latch based designs. This is because of the preponderance of microprocessor contributions to the total number of shipping transistors. So yeah, an artificial measure. In total there are relatively few people designing this way, but most processors use a scheme of:
Logic cloud -> latch (+'ve clock) -> logic cloud -> latch (-'ve clock) -> repeat semi ad-infinitum.
Which if you look at it is the canonical format for a master slave FF, but with more logic inserted between the master and the slave.
The vast majority of people, in terms of the total designs (as in number of designs)use single clock domain edge triggered. To quote Dally and Poulton (Digital Systems Engineering) "Edge-triggered timing, however, is rarely used in high-end microprocessors and system designs largely because it results in a minimum cycle time dependant upon clock skew". Use of latches driven by two-phase non-overlapping clocks results in very robust timing that is largely insensitive to skew. This adds in complexities in the design, signals from one clock domain cannot cannot be intermixed.
The other draw back is that it is rarely taught in schools.
If this was a question on high end system digital design. That would be your answer. If this applies to FPGA's - I don't know for sure but I suggest this COULD be the reason.
BTW - I'd suggest that book to anyone who is serious about advanced digital VLSI design.
"Dally, William J., and John W." Poulton. Digital Systems Engineering. Cambridge University Press.