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I need to know when the 14 MSB bits from the address bus of a z80 CPU are high. To do so my first idea is to use 4 74LS08 ICs (TTL AND gates) reading those lines but I don't know the maximum amount of current that can be drained from the CPU.

The 74LS08 has a maximum input current is of 0.1mA hence 1.4mA from the z80 but I cannot find the maximum z80 ratings on the zilog datasheet. The z80 datasheet mentions a TTL chip select decoder connected to the address bus but no mention of the IC ratings are given.

so, can I connect 14 TTL inputs to the z80 address bus without overloading the z80 outputs?

z80 datasheet
74LS08 datasheet

Clarification
One TTL input per address line, not 14 TTL inputs per address line.

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  • \$\begingroup\$ The datasheet you give only provides information on the Z80's instruction set architecture. The Z80 is a processor architecture, but there are like a zillion different second-source models and manufacturers of the Z80 in hardware, each with its own peculiarities. The electrical data for the particular chip you're using will be listed in the datasheet for that specific chip. \$\endgroup\$ – Bitrex Sep 6 '13 at 23:56
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    \$\begingroup\$ If you don't have much else on the bus it should be fine; if you are concerned you could consider a CMOS logic family with TTL-compatible thresholds. \$\endgroup\$ – Chris Stratton Sep 7 '13 at 1:56
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The Thomas Scherrer Z80-Family Official Support Page has a file called Z80 CPU DATASHEET (ZIP'ed PDF file) that contains some additional information on the DC characteristics of the Z80A. While it doesn't specifically mention a maximum that I can see at 250uA the minimum output high voltage is listed as 2.4V.

That should be a a good consertaive value as a few 74LS devices I checked listed 2V as the minimum input high voltage. Certainly if connecting 14 device inputs to a single output I think you'd need a buffer, however in this case when you have 14 different outputs going to 14 different inputs that won't be necessary.

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  • \$\begingroup\$ I intend to connect each of the 14 address lines to a separate AND gate input, no 14 inputs to a single line like P Bennet said. The voltage ratings seem withing spec unless I'm missing something important. Google books has a better version of that datasheet: books.google.es/… \$\endgroup\$ – NeonMan Sep 7 '13 at 0:48
  • \$\begingroup\$ I'd misread that part and thought you were trying to connect to 14 different devices to decode 14 different addresses. In your case it'll be fine, you'll only have problems trying trying to drive too many inputs from the same single output. \$\endgroup\$ – PeterJ Sep 7 '13 at 0:51
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When the Z80 was young, 74LS was the commonly-used logic family. You should be able to connect a few 74LS inputs (say 3 or 4) to each Z80 address line without problems.

If you really need to drive 14 74LS inputs from one Z80 output, you should probably add a buffer between the Z80 and your 14 inputs, so the Z80 only sees a single load on that output.

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  • \$\begingroup\$ One input per line but it is the aggregated current I'm afraid of. In any case, am early first-source Z80 should be able to tolerate that. \$\endgroup\$ – NeonMan Sep 7 '13 at 0:39
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A few 74LS138 (3 to 8 decoder) would be a better and easier solution than many 74LS08s. http://www.fairchildsemi.com/ds/DM/DM74ALS138.pdf (An ALS variant, but this is close enough).

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One or two TTL loads per pin is entirely acceptable for a Z80. More than that, read up in more detail...

I would use a pair of 74LS30s (8-input NAND) and a single NOR gate to combine their outputs, rather than a complex array of AND gates but they should work..

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  • \$\begingroup\$ I actually thought about that but 74LS00s and 74LS08s were what I had laying around. \$\endgroup\$ – NeonMan Sep 9 '13 at 23:16

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