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Background

I am developing a digital clock and data recovery circuit and am now getting into the evaluation phase, focusing on testing the limits of the design and finding potential strengths and weaknesses. An important metric of this particular design is the tolerance to jitter in the asynchronous input signal. To evaluate this metric, I have a test setup in mind as below.

schematic

simulate this circuit – Schematic created using CircuitLab

Problem

To ensure the results of the testing are meaningful, it is desirable that the jitter have these characteristics:

  • Random or pseudo random
  • Gaussian distribution
  • Standard deviation of noise is parameterized and can be swept (JITTER CONTROL above)

This doesn't seem like an easy thing to accomplish. Is there relatively simple way to inject a controlled amount of jitter into a test setup?


What I have so far

I've given it some thought and research and I have two potential ways to implement this in hardware.

  1. If the test circuit transmission clock is significantly higher than the DUT, then the output can be oversampled. Then, extra samples can be added or removed from the output to inject a discrete amount of jitter. This jitter won't be perfectly gaussian due to the quantization noise. But if the test circuit's oversampling rate of the transmission data is high enough, this concern can be mitigated.
  2. The test setup by Kubicek et al. (below) uses an optical transmission with a variable attenuator to achieve the desired effect. Its not at all obvious to me why this would achieve the above, but a spectrum analyzer should be able to determine if it works as intended.

enter image description here

I understand my question omits many details about the design and test setup. This is intentional as I want to keep this as conceptual and general as possible. I want to avoid this becoming a design-specific post in favor of creating a post of permanent reference value.

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One obvious answer is to use a digital signal generator to add a controlled amount of noise to the control input of a VCO.

Keep in mind that this noise signal will represent an instantaneous frequency error, rather than the phase error that you normally associate with jitter, so integrate/differentiate appropriately.

You show a separate circuit adding jitter to a clean signal coming from a test generator. The VCO could be part of a PLL in that separate circuit. The PLL will keep the average output frequency the same as the input frequency, but will have minimal effect on the added jitter as long as its feedback loop has minimal gain at the jitter frequency.

If you intend to generate more than a fraction of a unit interval of peak-to-peak jitter, you'll need an elastic store (FIFO) of some sort to hold the test data. It might be easier to just use the jittered clock to generate the data in the first place.

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  • \$\begingroup\$ I see, I see. I think using an NCO+DAC instead of a VCO might be easier for me. The NCO+DAC could drive the transmitter clock of the test circuit as you said. The test circuit itself would generate pseudo random jitter values which would then be used to calculate the NCO input. Your suggestion seems much more reasonable than Kubicek's wacky photo-attenuator. \$\endgroup\$ – travisbartley Sep 9 '13 at 4:49
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The test setup by Kubicek et al. uses an optical transmission with a variable attenuator to achieve the desired effect. Its not at all obvious to me why this would achieve the above

Your implied question is, "what is going on in Fig 5 to create controlled random jitter?".

First, realize that every optical receiver introduces noise to the received signal. This noise is quite accurately modeled as gaussian random current noise. The receiver's trans-impedance amplifier (TIA) stage naturally converts current noise to voltage noise. The photodiode/TIA output is an analog signal proportional to the optical input signal, plus the added noise we just talked about.

What's hidden in the drawing is a limitting amplifier to obtain digital logic levels from the TIA output. I guess this is happening in the fan-out buffer in the as-drawn circuit. When you apply a limitting amplifier to a noisy input, the noise will be converted to jitter, as there's variation in what time the rising and falling edges cross the decision threshold. This timing variation is jitter, and it's proportioanl to the noise at the input and inversely proportional to the slope of the edges (dV/dt).

As you increase the optical attenuation, you reduce dV/dt, but you don't reduce the noise, so you increase the jitter.

About the VCO solution

FM'ing your timing source (as suggested by Dave's answer) is not likely to produce gaussian random noise as you requested in your question. Certainly not random noise that's uncorrelated from edge to edge (random jitter or "RJ") which seems to be what you are after, and what you will get from the Kubicek circuit.

This is a good method to obtain frequency-swept sinusoidal jitter (SJ) which is another spec you need to worry about when characterizing a CDR. In fact it's much more common in my experience to spec CDR's by their tolerance for single-frequency sinusoidal jitter than for their tolerance to uncorrelated gaussian random jitter.

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  • \$\begingroup\$ Thanks for the explanations, they are helpful. What exactly is single-frequency sinusoidal jitter, and why is it more common than gaussian random jitter? Doesn't gaussian random jitter accurately model the jitter in real systems? \$\endgroup\$ – travisbartley Sep 10 '13 at 1:05
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One thing you can do is to implement a version of the delay circuit that is used in DLL's. This is typically a current starved inverter chain. You need to degenerate the current supply from the rails into the device and the current supply out of the device (for symmetry of rise/fall) and have a reconstruction inverter (w/o the current starving ) on the output.

This would also emulate the most common source of Jitter in sources (partial rail collapse and the being modulated onto the output through the G_m of transistors.

schematic

simulate this circuit – Schematic created using CircuitLab

The voltage controlled current sources can simply be PMOS and NMOS transistors but on a board you have other options. You can change the number of stages to increase the control of the delay voltage.

To contradict myself, you can also just control the upper supply as long as you keep the number of delay stages to an even number (being inverters they alternately will delay the the rising and then the falling edge). You would then need to have two reconstruction inverters on the output.

schematic

simulate this circuit

However, there is an even simpler way, if you just want to inject noise on the edges.

schematic

simulate this circuit

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  • \$\begingroup\$ I like this because of the simplicity. All that is needed is a long chain of inverters, a variable power supply, and a fanout buffer/inverter with fixed supply. Is there any advantage of using VCCS instead? I am aware of jitter in ring oscillators, and I can think of this as just an open loop ring oscillator. The conditions that cause jitter in a ring oscillator are the same that cause jitter here. \$\endgroup\$ – travisbartley Sep 10 '13 at 1:46
  • \$\begingroup\$ I just drew it as a Vccs because that is what is available. In a real DLL that is simply a PMOS on Top and NMOS on the bottom with an appropriate bias generator. BUt you question reminded me of a possibility, will add to the answer. \$\endgroup\$ – placeholder Sep 10 '13 at 2:53

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