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I plan to design a NAND flash disk using STM32F415RGT6 (168 MHz Cortex-M4) micro-controller. Using USB3300 PHY enables the microcontroller to connect in High-speed USB 2.0 mode. Therefore, the transfer rate of the physical layer should not be an issue. There are two requirements:

  • Transfer rate of the disk must be over 1 MB/s (both read operation and write operation).
  • A specific algorithm must be performed on the data before transfer it to/from the NAND chip (about 1100 cycles per 16 bytes = at least 70 MHz considering the 1 MB/s rate).

1) Is is possible to achieve such transfer rate using this micro-controller? The micro-controller supports DMA enabled data transfer for its USB connection.

2) How much processing power will be left for my algorithm? Has anyone measured their idle cycles after implementing a mass storage device in a micro-controller?

I know it is possible to implement such application using FPGA but I really like to avoid it if it would be possible.

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  • \$\begingroup\$ This question is hard to answer. The reality is unless someone here implemented this, you'll have to try it. 8Mbit/s doesn't sound too bad. Especially because the ST microcontroller has a NAND flash controller that'll speed up operations. \$\endgroup\$ – Gustavo Litovsky Sep 9 '13 at 17:52
  • \$\begingroup\$ I have purchased a STM32F4DISCOVERY evaluation board to estimate the number of cycles required for implementing mass storage device protocol and transferring the data between PC and NAND flash. But as you mentioned yourself, I was hoping that someone that has implemented such application on a micro-controller could provide some statistics. Even if their micro-controller was completely different (such as AVR) it would be very helpful. \$\endgroup\$ – Mostafa Sep 10 '13 at 2:46
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I have just implemented a FS usb connection on a STM32F3 (72Mhz). I dont' know for the HS rate, but about the number of cycle used by USB, I would say not so much.

I used an FSK algorithm which processed data all the time and take something like 75% of the CPU cycles, but the USB connection (VCP 115kbps) was ok and not disturb the algorithm, whithout DMA.

If you have the answer for the rate at HS speed, please post, it could interest me!

Seb.

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  • \$\begingroup\$ Thanks for the info. Assuming that data transfer in your design imposes 10MHz overhead, in the worse case scenario I would need less than 100MHz processing power for 1MB/s (considering that I am going to use DMA-based transfer the overhead should be a lot lower). I will post statistics of my own design as soon as I can. \$\endgroup\$ – Mostafa Sep 19 '13 at 12:10
  • \$\begingroup\$ Given that this differs from the need by a factor of about 69, I'm not sure it demonstrates much. But then VCP is limited to a very small packet size, so some efficiency could be gained by dumping that. \$\endgroup\$ – Chris Stratton Sep 19 '13 at 15:27
  • \$\begingroup\$ In the final design, I was able to achieve +7 MB/s during read operations using a 32 KB buffer. I believe higher transfer rates are possible by using a faster memory because USB stack is not the bottleneck. \$\endgroup\$ – Mostafa Mar 22 '14 at 9:47

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