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I have a failed on EMC Test 300MHz and 500MHz due to crystal harmonics. There is a lot of spike with a 25MHz harmonics. The first picture is the Top of the Board and the 2nd is the 2nd layer underneath the Crystal and the third one is the Bottom FPGA.

My crystal supplies two ICs (CPU and FPGA).I suspect the problem was due to bad layout and long path of the crystal output.

I want to know if this is really due to the PCB layout that causes the crystal to radiate. What are the parameters I violated? Your feedback would be helpful to debug this EMC issue.

  • \$\begingroup\$ Have you considered that the problem might be coming from signals derived from this clock source? \$\endgroup\$
    – Tut
    Sep 9, 2013 at 17:58

1 Answer 1


You should change your terminology to 'oscillator' instead of crystal. Oscillators are the type of component with an OE pin such as you have and require quite different layout requirements than those required by a crystal. We should also see the schematic of the oscillator connections and we should know the oscillator frequency.

In general your circuit and wiring for the oscillator should follow the sequence below:

a) Make sure that the oscillator circuitry is matched with a full pour GND plane under it.

b) Make sure to bypass the oscillator Vcc and GND connections in a way that there is copper without vias between the both sides of the bypass capacitor and the oscillator pins.

c) Keep the copper length between the bypass capacitor and the oscillator pins as short as possible.

d) Place a small value resistor in series with the oscillator output. The copper distance from the oscillator output to the resistor should be as short as possible. Resistor value can be determined from simulations done during signal integrity analysis or can be selected by value swapping on your prototype PCB and observing signal quality on a good quality oscilloscope.

e) Route the clock signal from the resistor to the nearest destination load and minimize the number of vias on the way. Best is no vias.

f) Continue the clock route from the first load as series layout. (Do not take the clock signal and route it as a branched Y to the two loads). The continued series connection is best if it simply passes through the pad of the first load. If a stub to the first load is required then keep it as absolutely as short as possible.

g) Route the series clock signal to the second load where it will terminate at the pad. Minimize the number of vias in the path. Best is no vias.

h) It can be an advantage to route the critical clock signal first in the layout so you can achieve the above goals. Then fit the remaining traces around this initial layout. Do note that the clock signal can couple to adjacent parallel signal routes in the same layer or in adjacent layers. You should check carefully that any adjacent signal routes are non-sensitive to some coupling, are not very long traces the go all over the board and are not signal lines that go off plane or out to I/O connectors. If parallel routes cannot be avoided then it may be necessary to impose minimum spacing design rules to help minimize the amount of coupling.


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