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I recently did a proper EMC test on a PCB of mine. It failed the test, and seems to be radiating in the 300MHz - 1GHz region, with peaks every 50MHz, and little peaks on the 25MHz.

Radiated emissions

Looking at the near field, you can clearly see lots of 25MHz harmonics around: Near field 25MHz harmonics

The board contains a 25MHz crystal, which must be the source of the signal, but the question is, what on the board is radiating? What could the antenna be? Candidates I can think of are:

  • The ground plane acting as a centre-fed patch antenna. The board is 23mm x 47mm, which makes it quarter wavelength for about 1.6GHz!
  • The inductors in the power supplies. The board contains TPS84250 and EN5312 integrated inductor switching power supply ICs. Perhaps the 25MHz signal is finding its way back to the inductors in these ICs and using them as antennae.
  • The cable. Although adding ferrites onto the cable during the test didn't seem to make any difference, which leads me to believe it's something on the PCB itself.
  • Something else? I can't think what else is large enough to radiate at such low frequencies.

The Equipment Under Test consists of a pair of PCBs stacked together. The bottom one contains the 25MHz crystal and the chips that use it. The top one contains the power supply components.

PCB PCB

PCB Layers

Question for bonus points: How can it be that there are clearly lots of 25MHz harmonics around in the near field, but only 100MHz and 50MHz harmonics are detectable in the far field?

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    \$\begingroup\$ Impossible to tell without at least a pic of the PCB layout (all layers). Schematics and the PCB stackup would also help. \$\endgroup\$ – user3624 Sep 9 '13 at 18:26
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    \$\begingroup\$ Was the test done with just the board sitting alone as pictured, or were there cables attached to it during the test? \$\endgroup\$ – The Photon Sep 9 '13 at 18:44
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    \$\begingroup\$ The good news is you see the source and you know basically that the 25MHz crystal and its harmonics are the issue. That sometimes is half the battle. Now the question is what is radiating this. Basically this is due to loops. Ideally you want a trace and its return path close so that their fields cancel each other. Otherwise you get a loop. As David said, we have to see layers to be able to tell you anbything. However, I can tell you that the crystal in the layout seems rather far from the Micrel IC. Pulling it close will reduce the loops. \$\endgroup\$ – Gustavo Litovsky Sep 9 '13 at 18:57
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    \$\begingroup\$ @Rocketmagnet - Putting a crystal on one side and the chip on the other is doable, but likely not the best option. The vias introduce inductance and capacitance which induce unwanted effects. \$\endgroup\$ – Gustavo Litovsky Sep 9 '13 at 19:37
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    \$\begingroup\$ I'll note that 1/10th wavelength is 640 MHz. You have a dominant peak @~ 600 MHz in the far field. I would be looking for fast edges with rise times on the order of ~ 1.5 ns. This will be your dominant emissive source. The 25 MHz side lobes are expected because the system has plenty of opportunities to mix in core frequency. For near field work, look to mix up E mode vs. H mode probes also. \$\endgroup\$ – placeholder Sep 10 '13 at 16:44
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This is a difficult problem to cover in a couple of hundred words, so this will be brief and you'll just have to do some research on your own. But I'll try to summarize it enough so you at least know what to research.

You need to know about trace impedance, signal termination, signal return paths, and bypass/decoupling caps. If you got these absolutely correct then you would have zero EMC problems. Getting it 100% perfect is impossible, but you can get much closer than you are now.

First, let's look at signal return paths... For every signal there must be a return path. Normally the return is on the power or ground plane, but it could be somewhere else too. On your PCB, the return is on a plane. The return path goes from the receiver back to the driver. The loop area is the physical loop created by the signal plus the return path. Normally the laws of physics will cause the loop area to be as small as possible-- but PCB routing wants to mess that up.

The larger the loop area, the more RF problems you will have. Not only will you emit more RF than you want, but you will also receive more RF.

The signals on the bottom (blue) layer will want their return path to be on the adjacent plane on the next layer (cyan)-- since that makes the loop area as small as possible. Signals on the top (red) layer will have their return path on the gold layer.

If a signal starts on the top layer then goes through a via to the bottom layer then the signal return path will want to switch from the gold to cyan layers, at the point of the via! This is a major function of decoupling caps. Normally one plane would be GND and the other would be VCC. A signal return path can go through the decoupling cap when switching between planes. That is why it is often important to have caps between planes even when it is not obviously needed for power reasons.

Without a decoupling cap between planes, the return path cannot take a more direct route and so the loop area increases in size-- and EMC problems increase.

But voids/splits in the planes can be even more problematic. Your gold layer has split planes, and signal traces, which create problems. If you compare the red and gold layers you will see how signals cross the voids in the planes. Every time a signal crosses a void in the plane then something is going to go bad. The return current is going to be on the plane, but it can't follow the trace across the void so it has to take a major detour. This increases loop area and your EMC problems.

You can place a cap across the void, right where the signals cross. But a better approach would be to reroute things to avoid this in the first place.

Another way the same problem can be created is when you have several vias that are close together. The clearance between the vias and the plane can create slots in the planes. Either decrease the clearance, or spread the vias out so a slot does not form.

Ok, so that's the biggest issue with your board. Once you understand that then you have to look at signal termination and controlling trace impedance. After that, you have to look at shielding and chassis GND issues with your Ethernet connection (not enough info in the Q to comment accurately).

I hope that helps. I really breezed by the issues but that should get you going.

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    \$\begingroup\$ Thanks for the great answer David. However, I'm fairly sure that the problem isn't return currents. Unfortunately, it's impossible to tell from the question, but none of the tracks that cross the plane splits are switching. I've taken great care to make sure that all high frequency traces have a proper return current path on their reference plane. \$\endgroup\$ – Rocketmagnet Sep 11 '13 at 23:27
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    \$\begingroup\$ Disappearing users are a mystery here I guess.. \$\endgroup\$ – Erik Friesen Sep 13 '13 at 22:15
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    \$\begingroup\$ @Erik Not necessarily: meta.electronics.stackexchange.com/q/3082/2028 \$\endgroup\$ – JYelton Sep 16 '13 at 23:56
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Having re-spun my board, the noise seems to be significantly reduced. I made quite a few changes, so it's difficult to know exactly which ones were responsible. Basically, I copied the EMC precautions used in the Beckhoff EtherCAT modules

  • Ferrites on all power pins of the ET1200 ASIC, with caps before and after the ferrite.
  • 5pF capacitor, two ferrites and common mode choke on the outgoing LVDS lines.
  • Improved crystal layout, with full ground plane underneath. I also followed Olin's advice regarding the connection of the crystal's load caps' ground.

As for what's actually radiating? It's hard to be sure, shielding the ET1200 itself didn't seem to help. Nor did adding ferrites to the cable. The only thing that did help was enclosing the PCB in a metal box. So I guess it was something on the PCB. Perhaps the ground plane acting as a centre-fed patch antenna as Olin suggested.

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I think the 25MHz harmonics point to ethernet related issues. I am not familiar with Micrel recommendations, but most other vendors recommend a minimum distance between phy and magnetics, which isn't apparent on your board. Also, there is a continuous ground plane underneath the magnetics, which also isn't recommended most places.

It is rather difficult to tell with the layout pictures, but it looks like the trace that runs underneath the phy then strings out and comes out as a nice antenna on the opposite layer. This could be confirmed with some near field probing, perhaps?

Things that show up in the near field and not in far, mean that there is no effective coupling path and antenna for that frequency, in my understanding.

Are you absolutely positive you have everything bypassed right? I had an emc tester tell me he had one board that went from not passing to passing because they had missed one bypass cap. You could also make sure your bypass caps are working the way you want at 25MHz. Use a spectrum analyzer with tracking generator and a 50 ohm stripline with caps solderered onto it, and see how they really are working.

I think David Kessner's answer is still worthy of consideration. I don't feel like we really have complete enough information here.

I think the very best would be to rent an hour or two with an experienced emc tech(maybe you have one inhouse), and absorb everything he tells you about your board.

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  • \$\begingroup\$ Thanks for the answer Erik. When you say "minimum distance between phy and magnetics", do you mean that they can be too close together? \$\endgroup\$ – Rocketmagnet Sep 12 '13 at 11:28
  • \$\begingroup\$ I'm not sure which trace you mean that runs under the Phy. Is it one of the ones on the gold layer? \$\endgroup\$ – Rocketmagnet Sep 12 '13 at 11:29
  • \$\begingroup\$ Yes, the gold layer. I assume you have them layed out like your stackup? Many say minimum of 1". I just did a design that was 1/2" and passed fine. See here as well - microchip.com/forums/m687729-p2.aspx \$\endgroup\$ – Erik Friesen Sep 12 '13 at 11:31
  • \$\begingroup\$ The track on the gold layer does go over continuous GND plane, with no splits (cyan layer). Shouldn't that help? Sadly the 1" distance is impossible with this design, as the whole board is 1" wide! \$\endgroup\$ – Rocketmagnet Sep 12 '13 at 12:35
  • \$\begingroup\$ I don't know, but from my experience with near field probing, I would say no. The phy, and between phy and magnetics is rather full of rf, I think that could very well couple in. Another thing, do you have any series resistor terminations on the mii(guessing here) lines? \$\endgroup\$ – Erik Friesen Sep 12 '13 at 20:38

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