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I have searched online, but I do not understand very well the procedure for reading from SRAM?

I have an exam about digital electronics and two of the questions may be what is an SRAM and how the reading process works for SRAM?

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It's pretty simple: You just apply the address to the address bus, make sure all the chip and output enables are in the right state, and the data appears on the data bus.

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    \$\begingroup\$ Top marks in the exam Mr T \$\endgroup\$ – Andy aka Sep 11 '13 at 15:00
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    \$\begingroup\$ Don't forget to wait for the propagation delay! (potential noob error when writing Verilog to do this) \$\endgroup\$ – pjc50 Sep 11 '13 at 17:42
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There are several different types of SRAM out there. Asynchronous, synchronous, parallel, serial, etc. ZBT, etc. It's not really clear from your question what you're actually dealing with -- a packaged chip? A die? A VLSI cell?

The interface changes significantly depending on what you're trying to deal with. At the core of the SRAM, however, there's an array of SRAM cells, which are generally made up of 6 transistors (6t cell) each. Basically it looks like two inverters feeding each other with two pass transistors on a word line. You get out a +/- bit line, which is fed into a sense amplifier. BTW compare this to a DRAM cell, which is 1 transistor and a capacitor...this is why SRAM is so much more expensive than DRAM (the most basic analysis suggests 6x area even though that's really just a swag and depends a lot on other factors).

The most basic interface from the IC level is probably the asynchronous parallel interface, which David Tweed alluded to in his answer. You need to be careful w/ timing -- especially propagation and board delay if your bus is fast.

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