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How do 5V-tolerant inputs work on a (3.3V or lower) device?

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  • \$\begingroup\$ In what particular context? Do you have a specific device in mind? \$\endgroup\$ – JIm Dearden Sep 13 '13 at 14:25
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    \$\begingroup\$ I have been using the STM32. \$\endgroup\$ – joeforker Sep 13 '13 at 16:31
  • \$\begingroup\$ I think this question needs more context to be a "good" question. \$\endgroup\$ – JYelton Sep 13 '13 at 20:36
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    \$\begingroup\$ IIRC the 5V-tolerant structure on some micros is an interesting, moderately complex structure that is actually powered by the higher-voltage input when it is present. \$\endgroup\$ – joeforker Sep 13 '13 at 20:53
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Most CMOS processes below 180 nm are double or even triple GOX (Gate Oxide) thicknesses. The thicker the gate oxide the higher the voltage withstand (same E - Field strength). A 180 nm process might have 4.5 nm GOX for the 1.8 V transistors and 90 nm Gox for the 3.3 V transistors. This will continue to scale down to 90 nm (so 0.9 V and 1.8 V I/O), below 65 nm is where the high K dielectrics start to be introduced so the scaling relationships change (of thicknesses vs. Voltage) with a 65 nm Gate able to have more voltage applied.

At around the 90 nm node, some processes have triple GOX to handle 0.9, 1.8 and perhaps 2.5 or 3.3 V inputs.

Going beyond a 2X scaling of core voltage to I/O voltage without additional process complexity means that you have to use circuit solutions to drop additional voltage before it gets into the core. These tend to be slower signals however.

Keep in mind that EOS (Electrical Over Stress) starts in at about 15% of applied voltage so the 0.9 V GOX really can have at most 135 mV additional voltage applied. So clamping diodes and the such will have far too much variability in knee voltage to be trusted. This shows the level of care that must be given.

Here is a rudimentary circuit solution (it gets far more complex): enter image description here

We will assume this is a 3.3V tolerant transistor.You can see that as the input S/D approaches the Gate voltage of 3.3V that the GOX has less voltage across it than the S/D on the inside S/D. Of course the spacing rules and sizes of the S/D's here must be increased to prevent Latch-up and other nasty stuff from happening. But the GOX should be relatively safe all the way up to 6.6V on the Input. As you go from the Input S/D along the length of the transistor the E-Field will decrease and then flip and invert to the opposite magnitude. But it is the size of the E-Field that determines breakdown.

If this transistor has Vth of 0.7 V, operated in this way (due to body effect) it's threshold will be ~ 1.2 V or so. The signal on the inside will not be a clean copy if you are expecting high edge rates. This is one reason why it is usually preferred to restrict the input voltages to the 2X factor mentioned above.

There is a lot more to this of course. Including using DMOS variants on the outer pad ring. This is just a small sampling.

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  • \$\begingroup\$ To what extent can semiconductor junctions be made to "leak" before they fail? If one were to connect the input of a gate such as you drew to non-voltage clamped a 1uA current source, would it start leaking 1uA at a voltage level low enough to prevent damage? Could one cascade transistors to allow higher voltages [with the gate of the first being constrained to no more than [breakdown] volts over the supply, no more than [breakdown] volts below the input, and no more than ~0.7 below the supply, or would that require additional processes? \$\endgroup\$ – supercat Sep 13 '13 at 16:43
  • \$\begingroup\$ There is a huge trade off space. At what part of the process do you put in extra steps? Extra wells, different structures etc. I touched upon that with the mention of DMOS transistors that support huge voltages by dropping the lateral field along the length of a larger drain structure. But they can only really be attached to the rails. Leakage in Si typically has a doubling constant of ~ 8 degrees so say you want to operate from 0 to 40 C, that is (40/8) = 5. 2^5 = 32. so the span of leakage currents will be 32X. There might be better ways of doing it ;) \$\endgroup\$ – placeholder Sep 13 '13 at 16:59
  • \$\begingroup\$ What you propose is what was done in 5V processes and the ESD clamp diodes. But the knee voltages are too variable for processes under 1.8V (that 15% thing in mentioned). Different techniques are used for ESD in those cases. \$\endgroup\$ – placeholder Sep 13 '13 at 17:01

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