# Spice definition of resistor/capacitor

I am trying to understand a Spice definition of a circuit and transient analysis on it. I have kind of "inherited" this and can't ask the original creator; my Spice memories from university are pretty rusty, and online manuals have not been of much help.

What I don't understand is the first segment here (snippet of whole file):

.define c1 6926.0 6233.4 7618.6
.define r1 0.16661 0.149949 0.183271
....
il   0 98 dc 0 ac 0 pwl (0s 1720.0a ... 6233s 1718.0a 6925s 1728.0a 7618s 1718.0a ....)
...
c01  1 0 [c1] ic= 89.974
r01  1 2 [r1]


In the third segment, I understand that capacitor c01 is defined as lying between nodes 1 and 0 and has initial conditions as given; resistor r01 is situated between nodes 1 and 2. In the second segment, a piecewise linear current source is defined, with ampere values associated with timestamps.

What does the first segment define? The values next to the capacitor seem to be the timestamps from the current source, but why are they used for defining the capacitor/resistor?

I can provide other details as needed, but didn't want to clutter the post too much with useless information.

EDIT: The suggestion given below in comments is good, but my original question still stands. Is this not standard Spice, since no manual mentions it?

• 6926.0 +10% = 7618.6 and 6926.0 - 10% = 6233.4. This may be a clue? Maybe something to do with Monte Carlo analysis? Commented Sep 16, 2013 at 10:08
• @Andy aka Thanks a lot, that sounds like something this circuit simulation is supposed to do!
– ACEG
Commented Sep 16, 2013 at 10:10
• Here is a *.pdf of the Micro-cap manual web.eece.maine.edu/~hummels/classes/ece343/docs/rm10.pdf Commented Sep 16, 2013 at 14:03
• @Cristina, There really is no "standard SPICE". Every SPICE has it's own variant syntax and capabilities. Even though you alrady got a solution, it would be very helpful for future readers to say in your question what SPICE you are using. Commented Sep 16, 2013 at 15:23
• @The Photon I think it is a proprietary variant developed in-house by our clients, so it unfortunately comes with confidentiality aspects attached -- I'm sorry I can't say more!
– ACEG
Commented Sep 17, 2013 at 7:18

Google search found that Micro-Cap Spice simulator does allow for .define keyword to be used.

I understand that .define could be omitted from the code you showed with the following change:

il   0 98 dc 0 ac 0 pwl (0s 1720.0a 692s 1726.0a 1385s 1716.0a 2077s 1720.0a 2770s 1726.0a 3463s 1724.0a 4155s 1712.0a 4848s 1720.0a 5540s 1724.0a 6233s 1718.0a 6925s 1728.0a 7618s 1718.0a ....)
...
c01  1 0 [6926.0 6233.4 7618.6] ic= 89.974
r01  1 2 [0.16661 0.149949 0.183271]


However, I've never seen this kind of syntax with square brackets (it neither seems to be supported by Micro-Cap). My guesses for this syntax are:

• Parameters value to be swept in simulation. If this is the case then I'd expect the simulator to sweep the value of $r01$ for each value of $c01$
• As suggested by Andy Aka this could be a part of Monte-Carlo analysis syntax. However, if there are no additional Monte-Carlo commands in this file - I'd say that this is not the case.
• Some kind of randomization syntax - the value of the component will be generated randomly from the distribution characterized by the numbers in the brackets.

I can try to narrow down the options (or provide additional ones) if you provide some more information.

Hope this helps.

• Thank you very much! Unfortunately, I cannot list the whole file, for reasons of confidentiality, but I can confirm that they do transient analysis on an RC circuit, followed by some sort of optimization (not ".mc", but ".optimize"...might be some proprietary brew I have hit upon!).
– ACEG
Commented Sep 16, 2013 at 13:42
• @Cristina in light of the fact that optimization of some kind is involved, I'd say that the values in brackets are the components' values to be tested when optimizing some parameter of the circuit. Commented Sep 16, 2013 at 14:09
• Thank you very much, I think this is enough to get me started, at least!
– ACEG
Commented Sep 16, 2013 at 15:09