Ethernet Layout Guidelines

Question

I'm working on a DC jack powered Ethernet design and I've downloaded many Ethernet Layout guidelines from many semi vendors with varying recommendations. I've read app notes recommending almost every possible termination resistor position, for example. Placing termination resistors at the PHY, at the Magnetics, the TX at the PHY and the RX at the magnetics, and visa versa. The most popular seem to be at the PHY, and this seems to make the most sense. Ethernet uses balanced differential pairs, which are typically terminated at the extremes to filter any common mode noise injected into the transmission lines, and the RX / TX traces on the board constitute part of the transmission line (these are being run at 100 ohm impedance to match CAT5 cable impedance).

The other controversy here is what to do with the ground plane. If this wasn't a DC jack powered app my life would be easier. Many app notes recommend no ground plane under the magnetics (which are built into the RJ45 connector in my case) to avoid coupling into the ground plane. But... that is exactly what I want. Better coupling into the ground plane then into the conformity testing antenna! A ground plane under the jack will help close the metal enclosure around the rest of the connector. I've read at least one example of anecdotal evidence on the net claiming better radiation performance with a solid ground plane in a DC jack application as opposed to a separate isolated Ethernet plane tied in with caps. So... I think I'm going to keep a solid plane under the RJ45 jack.

Some papers also recommend no plane under the RX / TX pairs. I can't make my mind up about this. I want to avoid coupling any ground noise into the RX and TX pairs but my experience seems to be any ground plane splitting / opening is usually based on hocus pocus type thinking instead of sound physics.

Does anyone here have any experience or suggestions related to Ethernet layout, specifically with regard to the RX / TX termination resistor placement and whether or not to use a ground plane under the RJ45 connector (with magnetics) as well as under the TX / RX pairs? Any suggestions greatly appreciated.

Answer 1

Look for application notes for your PHY and magnetics. The manufacturer would know best in regards to what works with their parts.

Generally there is no ground/power or routing under the magnetics and try to avoid ground/power under the TX/RX pairs. If you can't route the whole trace without a ground/power plane under it, leave the plane under it. It is worse if you go over a break in the plane.

For termination, check with manufacturers of the PHY and magnetics. Like you said, there are a few different schemes, the manufacturer should know best about their device.

We follow what I described above at work and don't have any problems with ethernet.

Answer 2

My understanding is you should NOT have a ground plane between the RJ-45 and XFMR due to the need for electrical isolation. Ethernet is supposed to withstand 1500V (lightning protection). The XFMR is rated to withstand 1500V (there's a split ground plane under the XFRM between digital GND and chassis GND). Chassis ground is stripped away from the ethernet traces on the cable-side for creepage/clearance.

Another reason is the XFMR has a common-mode choke to attenuate noise on both diff pairs (before the signal exits the board onto the cable, which makes a great antenna). You don't want digital ground plane underneath because the diff pairs will pick up more noise and cause you to fail

Here's the hard thing to understand. On a PCB, differential traces couple mainly to the reference ground plane and there is NOT much common mode rejection because crosstalk does not affect both traces equally. Most of the return current returns on the reference plane.

If a twisted-pair cable, the differential pairs have near 100% coupling with each other and therefore have extremely good common-mode rejection. The return current for one trace is on the other trace and vice versa.

Answer 3

Here is my final solution. The digital ground plane is filtered at the DC jack. The unfiltered plane is tied to the Ethernet jack and its ground. This will hopefully keep ESD off the digital ground and still provide a nice ground for the jack.

I ended up using a keepout area under the TX and RX pairs, so there is no ground plane under them.

The TX and RX termination resistors are placed close to the PHY (built into the PIC18F in this case).