# How to implement FIR filter for Altera DE2?

I understand that a DSP is preferred rather than FPGA for an FIR filter, but my task is to implement both fixed-point and floating-point software filters (in C) for the Altera DE2. I barely know what an FIR filter is so I must learn everything but I can program C and assembly and I know the hardware well enough to program hardware interrupts and I'm beginning to handle serial communication.

Can you give me some advice how to learn and get started writing the FIR filter? The spec is that

Samples are sent from a device source by a serial interface (115200 bits/second, 1 start bit, 8 character bits, no parity bits, 1 stop bit) to the receiver port of a UART that is connected by the Avalon-bus with the Nios-core. The Nios-core shall run a program that implements a FIR-filter with the coefficients

 c0       c1      c2     c3

0.0299  0.4701  0.4701  0.0299


The output samples of the FIR-filter shall be sent via the transmitter port of the same UART to another device sink.

I think I can solve the communication part (by means of the UART interface and putty(?) with a serial-to-usb cable to the DE2 board) but I'm not sure about the actual filter implementation and design. Can you help me? I want to look at designs for FIR filters to learn how to implement one.

• I understand but my spec is that it should be a software filter in C (even if real projects always do it in HDL) and I think it is so that I can learn what FIR filtering is the easiest way which could be coding it in C and comparing floating-point to fixed-point implementation. I think that one of the purposes of this task is the comparison between floating-point and fixed-point arithmetic. I don't know if HDL can implement both fixed and floating arithemtic (probably) but my sec says that my implementation should be in software and in C. – Niklas Rosencrantz Sep 17 '13 at 3:08
• The way you were told to do this (which is entirely reasonable when the source data is only coming over a 115200 baud link) involves using a soft core processor (the NIOS) in the FPGA. That makes it much more a generic embedded software problem, but much less an FPGA problem - possibly only one in the incidental issues of getting the system configured and running. – Chris Stratton Sep 17 '13 at 14:44

Since this appears to be homework, here are some general tips.

1. Check out the DE2 Manual to learn about the Avalon bus.
2. Read up on the Nios arctitecture.
3. Before you try to understand FIR filters, understand convolution.
4. Then move on to FIR filters.

And at that point, you'll probably see how to implement one. It boils down to multiply-accumulate operations, and manipulating a couple pointers. It won't take much since you already have your coefficients. The theory is the hardest part.

As you don't know anything about FIR filtering, start there. Get a good DSP book - Lyons is a good one to start out with: http://www.amazon.com/Understanding-Digital-Signal-Processing-Edition/dp/0137027419. Or you can read Smith's DSP guide online: http://www.dspguide.com/. Implementing a FIR filter is actually straightforward once you have the theory, you just shuffle through an array of past data values, multiplying them by some numbers and adding all the results up.

Build a software implementation on the PC, make it a single function that takes in a sample at a time, filters it and returns the filtered value. Call that in your main() function which takes data from a file and writes it out to a file.

Once you have that working, build the Nios part which will take the samples in. For now just return them back out unfiltered. Once that part is working, you can insert your FIR filter from the PC version. Move the code into the Nios environment, it should port relatively easily. Apply the filter to the incoming data stream and send the returned values back out of the serial port.