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I have a design where i am using TPS53355 from TI to generate 0.9V @ 15A from 12V(10V-14V). For this design, i want to know whether RC Snubber required or not?

as far as i know,

Generally in High current converters inductor will store lot of energy = (1/2)*L*i^2.

If there is a gap between upper MOSFET(Control MOSFET) Off and Lower MOSFET(Sync MOSFET) ON, whole energy stored in inductor will be collapsed suddenly, can develope large spike on LL pin of V = L* di/dt.

In our case, L=0.47uH, Imax = 15A, energy stored in inductor will be = 0.5*0.47uH*15*15 = 53uJ.

I am not sure in the case of TPS53355, whether any delay between Control MOSFET OFF to SYNC MOSFET ON and the rise and fall times of MOSFET driving circuitry.

if Control MOSFET turnOFF time is approx 50ns.

then V = 0.47uH * 15A/50nSec = 141V. then this much voltage(141-12) has to be withstand by internal MOSFET for the duration where Control MOSFET is OFF and before Sync MOSFET turns ON. Generally Internal MOSFET's will not have higher breakdown voltages due to their space constraints. How we can be sure that internal MOSFET will not damage for this spike.

in the datasheet of TPS53355, i didn't find these details regarding timings of Turn ON and OFF,But the recommended circuits have Snubber placed in.

There is "Dead time" between Control MOSFET oFF to Sync MOSFET ON to reduce any shoot through. any details regarding this also helpful.

**One more question is, In one of the literature, i read that due to parasitic effects of inductor and capacitor we will have spikes at the switching node (here LL), But i thought because of sudden change in current, voltage spikes will occur at the switching node, am i correct* .*

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3 Answers 3

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Have you considered that the parasitic diode inside the lower mosfet (in a synchronous buck) will conduct and reduce the projected (-)141V you mention? There is also the parasitic capacitance of the inductor which will also tend to reduce this "spike" and convert it to a decaying sinewave until the lower mosfet turns on.

Regarding your "one more question" I think a link may be missing (here LL)?

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  • \$\begingroup\$ "LL" switching node of TPS53355. Sorry for the confusion. \$\endgroup\$
    – user19579
    Commented Sep 18, 2013 at 9:39
  • \$\begingroup\$ @ Andy Aka: Sync MOSFET's internal diode you mentioned, whether it is fast enough to turn ON and whether it can able to handle that much current (14A) for short duration ? \$\endgroup\$
    – user19579
    Commented Sep 18, 2013 at 12:07
  • \$\begingroup\$ @user19579 I've just been looking at the chip and it strikes me that when the top FET switches off, if there is too much of a negative voltage on LL then this FET will start to switch back on again and ensure LL cannot go too far negative. Any doubts you may still have I'd consider mitigating by adding an external schottky from LL to gnd. \$\endgroup\$
    – Andy aka
    Commented Sep 18, 2013 at 12:28
  • \$\begingroup\$ @ Andy aka sorry if i ask multiple times, " top FET switches off, if there is too much of a negative voltage on LL then this FET will start to switch back on again and ensure LL cannot go too far negative." this looks very new, any link may help. " I'd consider mitigating by adding an external schottky from LL to gnd."--> putting schottky diode will make it as non-sync buck converter, \$\endgroup\$
    – user19579
    Commented Sep 26, 2013 at 4:30
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    \$\begingroup\$ @user19579 adding a diode (like in a non-sync circuit) will not mean it doesn't behave like a sync and have the efficiency of a sync. The diode will catch what the FET doesn't while they are both switched off. \$\endgroup\$
    – Andy aka
    Commented Sep 26, 2013 at 7:08
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For a synchronous buck operating in continuous conduction mode (CCM) a snubber at the switching node is not needed.

However, there is also discontinuous conduction mode (DCM) and burst mode in synchronous bucks operated at light load. In DCM and burst operation the switches are off and the switching node will ring by the interaction between the output capacitor voltage and switch output capacitance (\$C_{\text{oss}}\$) through the buck inductor (L). So, for these two modes you would want a snubber at the switching node. The most simple type of snubber is a series RC from ground to the switching node. Snubber capacitance should be about 5 times \$C_{\text{oss}}\$, and resistance is best to equal \$Z_o\$ of L and \$C_{\text{oss}}\$.

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Now i have read few application notes from TI, STmicro and other sources.

I found that Phase(SW) ringing is not completely due to sudden collapse of inductor current, as Andy said, during the dead period, the Sync MOSFET's body diode will come into action for short duration when inductor collapses.

When the sync MOSFET turns ON, inductor energy will expended into load and parasitic elements, and actual problem comes when the Sync MOSFET turns OFF and Control MOSFET turns ON, in this dead period again Body diode will active and when Control MOSFET turns ON because of bad reverse characterstics of Body diode, parasitic inductors, Fast Turn ON of Control MOSFET and Output capacitance(Coss) of Control MOSFET(during OFF state)(LCR circit) will resonate giving ringing at the SW node.

Which can be mitigated by different methods 1. Perfecting Layout so, that parasitic effects are minimised

  1. adding a BOOT resistor in series with BOOT capacitor which slow down the Turn ON of Control MOSFET

  2. Adding a series Resistor to control MOSFET's gate which slow down the Tur ON of COntrol MOSFET.

  3. As Andy said adding Schottky diode as Non-sync Buck converter(it will share the current during dead period only)

  4. Adding RC snubber

  5. Adding RL circuit to the COntrol MOSFET's drain

  6. Adding CSI(Common source Inductance)

few links regarding this. 1. Controlling switch-node ringing in synchronous buck converters

  1. Ripple reduction Techniques for High performance NexFet MOSFET

3.Phase Node Ringing - Has good quatitative analysis

from other posts, i found that body diodes can handle good amount of power(initially i doubted whether body diodes can able to handle full inductor current in dead period)

EMI generated because of this has more or less 3 factors.

  1. Low frequency conducted noise (<30 MHz)- Swicthing freq harmonics

  2. broadband noise (50 – 300 MHz) from the phase voltage ringing(due to parasitic elements and Coss)

  3. high frequency noise (>300 MHz) as a result of Sync MOSFET's body diode reverse recovery I am using BOOT resistor.

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