This is a follow-up question to this one.

I would like to investigate the effect of the gate oxide thickness Tox on the leakage current. To this end, I ran a set of SPICE simulations and plotted the obtained data: The leakage current vs. the gate oxide thickness

Now, I am trying to find an explanation to this curve. As far as I know, leakage should increase exponential as Tox decreases; this can be seen on the left-hand side of the plot. However, a similar behavior can be seen also on the other side. So, the question is: What is going on on the right-hand side? Thank you.

UPDATE 1: The observed behavior seems to be what is described in the first paragraph of this section.

UPDATE 2: Using the notation introduced here, the following pictures displays the currents flowing through each of the four voltage sources (divided by two as there are two inverters in the circuit):

All the currents

UPDATE 3 (by Vasiliy): Using the model file provided by Ivan I simulated the circuit and measured currents at all terminals of all the transistors separately.

Few clarifications:

  • Negative current means that the current is flowing out of the respective terminal.
  • Purple curve - Gate current
  • Navy curve - Source current
  • Cherry curve - Drain current
  • Green curve - Bulk current
  • Drain and Source currents overlap on the last graph (NMOS of the second inverter). Seems very strange as the polarity of these currents must be opposite. I double checked the Spice code, but it seems fine. Still, treat the last graph with care.

Inverter 1 PMOS currents

Inverter 1 NMOS currents

Inverter 2 PMOS currents

Inverter 2 NMOS currents

UPDATE 4: Please right-click on the graphs and choose "Open Image in New Window/Tab" to see them in full size.

  • \$\begingroup\$ Could you provide the schematic of the setup or the spice code that generated this trace? \$\endgroup\$ – Vasiliy Sep 18 '13 at 11:03
  • \$\begingroup\$ @Vasiliy, it is the same circuit as we discussed. The only difference is in the models that I use, and I tried to explain this part in response to one of the answers below. My model card is this one wherein I vary Toxe, Toxp, Toxm, and dTox preserving the same relationships as in the default configuration. \$\endgroup\$ – Ivan Sep 18 '13 at 11:33
  • \$\begingroup\$ @Vasiliy, forgot to mention that, since I could not find a command to sweep Tox, I had to change the model card itself for each point. \$\endgroup\$ – Ivan Sep 18 '13 at 11:37
  • \$\begingroup\$ So this graph is not just gate leakage, but the sum of gate + subthreshold leakages? \$\endgroup\$ – Vasiliy Sep 18 '13 at 12:21
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    \$\begingroup\$ I added plots of the currents of all the transistors in the circuit. \$\endgroup\$ – Vasiliy Sep 25 '13 at 20:56

From the graphs we see that gate leakage currents of all transistors decrease with increasing \$T_{OX}\$. This means that the increase in total leakage current must be attributed to subthreshold conduction.

Why would subthreshold current increase? The following equation for subthreshold curent appears in BSIMv4.7 User's Manual:

enter image description here

While there are many parameters involved, the main suspect is the treshold voltage, \$V_{th}\$, which is known to be sensitive to gate oxide thickness (as well as almost any other transistor's parameter).

In order to verify this I built the following circuit:

enter image description here

Sweeping \$T_{OX}\$ and measuring \$V_{th}\$ resulted in:

enter image description here

This linear decrease in threshold voltage explains an exponential increase in subthreshold leakage (based on the above equation).

The natural continuation of the answer would be to explain why \$V_{th}\$ decreases with \$T_{OX}\$. The equation used to calculate the threshold voltage for BSIMv4.7 model in Spice is:

enter image description here

\$T_{OX}\$ dependence appears in the above equation both explicitly (TOXE) and implicitly (through other parameters which depend on \$T_{OX}\$). It is beyond my expertise and knowledge to perform this task and map various numerical parameters into physical effects taking place in the actual transistor.

In summary:

The reduction in threshold voltage due to thicker oxide leads to higher subtreshold leakage current. The exact effects which cause the reduction are very complex.

  • \$\begingroup\$ From your write up with reference to Vth " ... which is known to be sensitive to gate oxide thickness " Which is a very strong statement to make. You have given the BSIM Vth formulae, the least you can do is to point out within that formulae how Tox modulates Vth. Unless you do that you've just restated the original question or at least substantiated that the model has that characteristic. Hint: you should be able to research the names of the variables like K3 etc. \$\endgroup\$ – placeholder Sep 26 '13 at 22:07
  • \$\begingroup\$ @rawbrawb, even the simplest model of \$V_{th}\$ incorporates \$T_{ox}\$ dependency (the "usual" dependency). I don't see why you consider it a "strong statement". I think that I did more than "the least I can do" in answering this question. I used all my knowledge and expertise and brought out the facts in simulation. I know what is "over my head" though, therefore I admit that parsing this very complicated equation is beyond my competence. You are welcome to perform this task and post it as an answer - I'll be glad to learn something new. \$\endgroup\$ – Vasiliy Sep 27 '13 at 8:07
  • \$\begingroup\$ @Vasiliy, thank you for the great answer! A technical question and, probably, rather trivial for you: how did you measure the threshold voltage? \$\endgroup\$ – Ivan Sep 27 '13 at 8:25
  • \$\begingroup\$ @Ivan, my Spice simulator allows for this syntax .print dc vth(mNMOS). I'm not sure that this is a standard feature across Spice simulators. The advantage of this approach is that it is very easy to obtain the threshold voltage, and the value obtained is the exact numerical value used by the simulator during analysis. There are several techniques which are used to measure the threshold voltages of real transistors which can also be employed in simulation analysis - google it if you're interested. \$\endgroup\$ – Vasiliy Sep 27 '13 at 8:34
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    \$\begingroup\$ The other irony, is that I was dropping hints, in the last question and this question's comments hoping that you'd pick up the ball and run with it. You're clearly interested. \$\endgroup\$ – placeholder Sep 27 '13 at 15:00

I will interpret this question as "why does changing the Gate Oxide thickness modulate the S/D leakage current" i.e. why does the effect exist in the BSIM model, what are the physical processes involved in this occurrence.

This is a paradoxical result (explained later) and arises from the extreme scaling effects of small transistors.

Summary: Barrier lowering from short channel effects due to the design of the transistor. This barrier lowering reduces the effective \$V_{TH}\$ which increases the \$I_{DS}\$.

Housekeeping: The OP has not stated enough information in order to answer this question so I will state my assumptions and reasons for these assumption first.

  • I am assuming that these are pocket (i.e. halo implanted - more details later) transistors.

  • This is a reasonable assumption because at any process node below 180 n you can't get enough gate control or yield from a non-pocket transistor.

  • we also have hints that this is concerning small transistors because the OP is dealing with BSIM 4 which came into existence for transistors in process nodes of 90 nm and below.

  • we also see the \$I_{DS}\$ modulation with \$T_{ox}\$ effect that implies a maximum \$V_{TH}\$ which decreases with changes in effective channel length away from an optimal. This is classical pocket transistor behaviour. Classical long channel MOS FET cannot behave that way.

  • and the oxide thicknesses are in the range of oxides used (unknown material however) in process nodes that are in 65 nm and below range.

  • Attribute for copied images are in the image descriptor in source.

If you have a long enough transistor (i.e. S/Ds do not influence the channel) there is no expectation that a change in \$T_{OX}\$ should change the the \$V_{TH}\$. The threshold will be affected by the work function of the gate, the doping level of the channel/Well, surface traps and fixed charge in the Oxide. This is evidenced by a classical dependance of \$V_{TH}\$ curve seen below. The Threshold voltage is a flat line as the length increases.

Grabbed from sciencedirect.com

But clearly this effect is happening in smaller transistors. To understand this you have to understand some of the design details of modern transistors. In order for short transistors to work they must have the following characteristics as shown below. (I've mangled the data a bit to quickly get it into excel - my apologies)

enter image description here \$V_{TH}\$ vs. Physical Length - [V vs. um] c/w halo implant

Underneath the the S/D implants are some specialized implants called halo implants which increase the well doping locally in front of (towards the channel side) the S/D implant.

Without the Halo implants the transistor at these small dimensions would have the following characteristics.

enter image description here \$V_{TH}\$ vs. Physical Length - [V vs. um] w/o halo implant

copied from Robert Wittmann PHD thesis

With a Halo implant, the channel is no longer uniformly doped along it's length. The surface charge density varies with position. The end result is that the transistor is much more manufacturable. In the second drawing above you will see that if the channel length is modulated (say through LER - Line edge roughness) that the transistor stays at roughly same threshold. So process variations around a nominal gate length will yield nominal \$V_{TH}\$ the third drawing (without Halo) shows an increasing \$V_{TH}\$ for longer channel lengths and more variation of \$V_{TH}\$ with change in L.

It also helps reduce the influence of the S/D on the channel and gives the gate more control. This means that the S/Ds can be brought close together without adversely affecting the \$V_{TH}\$ . Thus the transistor is smaller (but do keep in mind that 10's of nm are being fought for here). As an aside, this now necessitates new implants like a APT (Anti-Punch-Through) implant to prevent the S/D from joining depletion regions together under the channel. But that is another story.

The physical model is thus: As \$T_{OX}\$ increases the gate loses some of it's control over the channel. The fringing fields from the gate in the sidewalls/spacers above the LDD extensions does not have as much ability in its fight with the S/D implants for control of the channel, that lowers the barrier which effectively lowers the \$V_{TH}\$.

I recommend getting "Tsividis, Yannis". Operation & Modeling of the MOS Transistor. 2nd ed. McGraw-Hill Companies, 1998. (probably a newer version would be better) for any one at all interested in transistor physics. From that edit, page 263 here is a scan:

enter image description here

This discusses the modulation of \$V_{TH}\$ with length. In particular the \$ \frac{t_{ox}}{L}\$ term is very interesting. It says that length modulation is the same as oxide thickness modulation. Here the question is what is happening with thickness change, the answer is the gate is surrendering control. The same effect of the same magnitude can be obtained with a length modulation. It is totally about the fight between the S/D control of the channel vs. the Gate control of the channel.

  • as an aside -> test the model -> increase the length at the same time you are increasing the oxide thickness in your models.

This effect is related to DIBL - (Drain Induced Barrier lowering) which arises from the drain region depletion region expanding because of higher voltage which then starts to take over control the channel.

This is a complex subject, it is not covered in text books, but in research and published articles and I have hardly done justice to the nuances involved.

  • \$\begingroup\$ This great question deserves more than speculative guesswork and "hand waving" explanation of HALO: 1) Your assumption about HALO implants is not justified 2) 90% of your answer concerns Gate's length variation, which is irrelevant to this question 3) Your "physical model" is simply a "hand waving" 4) Did you run any simulation at all to verify what you write? In general: in the body of the question and his comments OP provided enough information, including references to Spice models and manuals. \$\endgroup\$ – Vasiliy Sep 27 '13 at 7:59
  • \$\begingroup\$ Thank you for the answer. I consider a 45-nm technological process and use the model cards of the predictive technology model (PTM) developed in Arizona State University. According to the manual, more precisely, Section 2.3 titled "Non-Uniform Lateral Doping: Pocket (Halo) Implant," BSIM4 is capable of modeling the phenomenon that you described in your answer (as far as I can tell). Let me please ask: what do you sweep on the X axis? Is it the channel length or the effective channel length? \$\endgroup\$ – Ivan Sep 27 '13 at 8:40
  • \$\begingroup\$ @Ivan, just to save your time: BSIMv4.7 model is capable of modeling non-uniform lateral doping, but, since both LPEB and LPE0 parameters are set to 0's in the particular instance of the model you've used - this answer is, probably, irrelevant to the simulation results which led you to ask this question. \$\endgroup\$ – Vasiliy Sep 27 '13 at 9:55
  • \$\begingroup\$ @Vasiliy you fundamentally misunderstand what short channel effects means - I will edit my answer to add this material. You're clearly interested so this is good feedback into what is lacking. As to the arm waving, well you clearly haven't read up on how transistor effects are derived ... but more importantly, there isn't room here for 100 pages, all I can hope for is that the interested party then has enough ammo and a physical model help guide their own in depth search. \$\endgroup\$ – placeholder Sep 27 '13 at 14:30
  • \$\begingroup\$ @Ivan I sweep length - sweeping effective length would be - well strange as it is an abstraction used to understand effects. here we are looking at isolating one effect. I'll clean that up. As an aside, you comments on process should be folded back into the question itself, not everyone reads comments (myself included) and comments are expected to eventually go away - purge by the system. Salient information should be moved into the question itself. \$\endgroup\$ – placeholder Sep 27 '13 at 14:33

If you are using a transistor model for these simulations then you are probably making an invalid assumption. A given transistor model is only designed to provide accurate results for the given transistor being modeled. Changing model parameters such as \$t_{ox}\$ beyond the range of values that are actually expected to occur in a given transistor model may give you wildly inaccurate results.

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    \$\begingroup\$ I am using BSIM4 configured according to PTM, namely, according to 45nm PTM HP. The assumed values are spread around the default one (1.25nm) found in PTM. Also, the manual of BSIM4 (page 5) confirms that this range is rather reasonable. \$\endgroup\$ – Ivan Sep 18 '13 at 11:25

It is possible that as the gate oxide layer increases in thickness, the field from the gate voltage decreases and the transistor is not cut off so hard. If so, a more negative gate voltage (assuming N-type) would reduce leakage at the RH side and shift the minimum to the right.

  • \$\begingroup\$ Thank you, Brian. I have found something similar in the first paragraph of this section. May I please ask you to have a look and confirm. \$\endgroup\$ – Ivan Sep 18 '13 at 11:49
  • \$\begingroup\$ to be honest that's far enough from my expertise that I can't confirm it with any level of confidence. \$\endgroup\$ – Brian Drummond Sep 18 '13 at 14:05
  • \$\begingroup\$ Sorry for this misunderstanding. I was asking for a different kind of confirmation: I wanted to clarify if your explanation was the same as the one in Wikipedia. It is the same, right? \$\endgroup\$ – Ivan Sep 18 '13 at 15:04
  • \$\begingroup\$ I can't be sure. I was hoping one of the process experts would join in... \$\endgroup\$ – Brian Drummond Sep 18 '13 at 15:08
  • \$\begingroup\$ @BrianDrummond, I think your intuition tricks you this time. Thicker gate oxide means smaller capacitance which reduces the charge density in the channel for a constant voltage. The reduced charge density leads to a reduced conductivity, therefore, using the most simplified MOSFET model, the current should've been lower. Your answer could (theoretically) apply yo depletion mode transistors, but this is not the case here. \$\endgroup\$ – Vasiliy Sep 19 '13 at 19:32

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