I found some information about general creepage and clearance distances here but it doesn't mention what is OK for inner layers, which are insulated and not subject to contamination the way outer layers are. Anyone know of a good reference for clearance rules for inner layers? I need to support 500V isolation.
I would recommend the IPC: IPC2221A. They are conservative BUT most testhouses that then underwrite your design will only do so against the IPC. The IPC2221A become very annoying for uncoated terminals, especially at elevation. Personally I have been using the British Standards for uncoated clearance (for elevation & pollution) with an additional factor on top.
For voltages greater than 500V, the (per volt) table values must be added to the 500V values. For example, the electrical spacing for a Type B1 board with 600V is calculated as: 600V - 500V = 100V 0.25 mm + (100V x 0.0025 mm) = 0.50 mm clearance
One thing to be clear though is when you say 500V do you mean?
Peak working voltage
Repetitive transient voltage
Dirac pulse voltage
- Repetitive Dirac pulse voltage (eg switching spikes)
The ones marked with * are the ones you should be using to determining the voltage to derives clearance. The only one that isn't Dirac pulse voltage that isn't repetitive (you will have to define what you class as repetitive) & if you see some high spikes then the dielectric breakdown of the FR3/Prepreg will have to be used.
On the topic of prepreg, I would advise the use of double prepreg IF it is to be used to separate high potentials. Even though prepreg at the standard thickness used should in theory provide 4kV of voltage withstand, there have been some annoying instance of poor quality prepreg or poor handled prepreg causing breakdown.
NOTE it really should be creepage, not clearance.
Creepage is the separation between two conductors as measured along the surface/layers of a board.
Clearance denotes the shortest distance between two conductive parts as measured through the air.