What is the difference between Buried Photodiode and Pinned Photodiode? I understand that the P+/N/P structure where the P+ and P layers have the same potential is the Pinned Photodiode. So what is the buried Photodiode?

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    Is this a "pinned" photodiode or a PIN (P/Intrinsic/N) photodiode? – Brian Drummond Sep 21 '13 at 13:41
up vote 4 down vote accepted

This is a commonly misunderstood misused set of terminologies.

First off these are not PIN Photodiodes - which stands for P - Intrinsic- N. These have large depletion regions for higher internal QE (Quantum Efficiency) and faster response. You can't make an array with this design though.

Pinning, refers to fermi-level pinning or pinning to a certain voltage level. Or also the forcing or prevention of the fermi-level/voltage from moving in energy space.

You can get surface state pinning from the dangling Si/SiO2 bonds providing trapping centers. A buried PD (Photodiode) has a shallow implant that forces the charge carriers away from these surface traps. The Si/SiO2 surface contributes to increased leakage (dark current) and noise (particularly 1/f noise from trapping/de-trapping). So confusingly a buried PD avoids pinning of the fermi-level at the surface.

A pinned PD is by necessity a buried PD, but not all buried PD's are pinned. The first Pinned PD was invented by Hagiwara at Sony and is used in ILT CCD PD's, these same PD's and the principles behind this complete transfer of charge are used in most CMOS imagers built today.

A pinned PD is designed to have the collection region deplete out when reset. AS the PD depletes it becomes disconnected from the readout circuit and if designed properly will drain all charge out of the collection region (accomplishing complete charge transfer). An interesting side effect is that the capacitance of the PD drops to effectively zero and therefore the KTC noise \$ q_n = sqrt(KTC) \$ also goes to zero. When you design the depletion of the PD to deplete at a certain voltage you are pinning that PD to that voltage. That is where the term comes from.

I've edited this Answer to acknowledge Hagiwara-san's contribution. It has long been incorrectly attributed to Teranishi and to Fossum (in CMOS image sensors)

  • "QE"? <padding> – jippie Sep 21 '13 at 15:10
  • @jippie Explanation added - thanks – placeholder Sep 21 '13 at 15:15

The first Pinned PD was not invented by Teranishi at Sony. Teranishi was not in Sony. He was in NEC.

The first Pinned PD, in the form of P+NP sensor element on Nsub structure with the N layer floating for complete charge transfer, was invented and filed in Japanese patent by Hagiwara at Sony in 1975, and was used in his FT CCD imager in 1978 with P+NPsub sensor element, in which both P+ and P are connected.

Later, Teranish at NEC disclosed his ILT CCD PD's later, Sony introduced HAD sensor, P+NPNsub photo elemnent video camera on the market. Sony now enjoing the big sensor business with the back illuminated CMOS imager with the HAD sensing element which was Hagiwara's invention.

Confusingly, HAD sensor and the pinned PD, Teranish's ITL CCD PD's, and Haiwara's P+NP transistor structure on the Nsub are all the same thing. And the VOD punch thru mode waas naturally expected by Hagiwara' original 1975 P+NPNsub photo sensing element structure patent. So who is the inventor?

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    Welcome to EE.SE! This information is interesting, but it is not a direct answer to the question at the top of the page. Would you please edit this to address the actual question? – Dave Tweed Jun 3 at 14:46
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    It is important that this reply stand for context and to correct for a historical error and misreporting. One cannot understate the importance of how significant his techniques and efforts have been. Even if this doesn't align with the EE.SE . In the previous form of my answer, I was reporting on the narrative that has been promoted in the image design community. Attribution is imortant. – placeholder Aug 16 at 19:20

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