I'm trying to build a circuit to simulate a dice roll using a 555 in astable as it's heart. The output pulses are counted by a 4026 and then fed into a 4511 BCD to 7 segment decoder.

It works perfectly and counts from 0-9, but I cannot get it to reset at 6 and start from 1.

I have tried to take jam input 1 high and then take the preset enable pin high when the counter hits 7, but nothing happens. I did this by using a quad input AND gate. Inputs 1, 2 and 3 were the binary code for 7 (1110) and input 4 was the clock signal inverted, so it would only work when the clock was off. This did not work and it just got stuck on the number 7 without resetting.

Have any of you had experience with this type of circuit? What can I do?

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    \$\begingroup\$ Can you provide a schematic? \$\endgroup\$ – Renan Sep 21 '13 at 16:53
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    \$\begingroup\$ I second Renan here. Also your question is confusing as the 4026 datasheets I have found indicate that the 4026 outputs directly to 7 segment displays. You seem to have the right idea of detecting a state to reset the device., a schematic/ more details will help. \$\endgroup\$ – placeholder Sep 21 '13 at 17:51

The counter, i.e. 4026, that you specify is a device already containing the 7-segment decoder. Plus this counter is not really suitable to the application where you want it to count from 1 through 6.

Instead look at using a counter such as a 74HC161. This can be hooked up as shown below to make it count from 1 through 6.

enter image description here

This circuit will count from up to 6 (i.e. the state where QB and QC both come to 1's in the output count. The 74HC00 NAND gate will detect this condition and force the synchronous LOAD input active low. On the next clock pulse from the 555 chip the counter will reload to a value of 1 (Inputs D C B A in the 0001 binary state) as opposed to advancing to a count of 7. Subsequent clocks will then count 1->2, 2->3, 3->4, 4->5, and 5->6 where the reload cycle will repeat itself.

Note that at initial power up this circuit may have an initial value in QD QC QB and QA that is outside of the range of 1->6. If this happens it is just necessary to let the clock run till the counter advances to a state where QB and QC are both 1's. If this behaviour is unacceptable then is is necessary to design in an additional signal that low ORs in with the output of the NAND gate to initially force the counter LOAD Input low for one or more clocks from the 555.


You can use a three input AND gate .Connect the A1 with a , B1 with b and C1 with c.Then connect the output with reset pin of 4026

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    \$\begingroup\$ What happens when the counter displays the digit "3"? The same segments that you have decoded for the digit "7" are illuminated and the counter resets. In other words, this solution doesn't work. \$\endgroup\$ – Dwayne Reid Feb 21 '15 at 21:40

I have successfully managed to reset the 4026 when it reaches 6. One important thing that should be noted: you DO NOT need the 4511 IC due to the built in decoder in the 4026 counter.

The answer goes as follows:

  1. Make the typical connections for the 4026 IC, like Vcc, ground and 7 segment display pins connections. 

  2. Invert the output of PIN 9 ( d ) using a NOT gate.

  3. The output of the inverter goes to a 2-input AND gate.

  4. The second input for the AND gate is from PIN 10  ( a ) without any inversion ( direct connection ).

  5. The output of the AND gate is then connected to PIN 15 ( reset ) through a 4.7k ohm resistor to prevent any false triggering ( I have spent hours to figure the false triggering issue out)


I have selected ( a ) and ( d ) to trigger the RESET to high when the counter reaches 7. Thus, the IC be will reseted after completing 6. This specific combination ( a and d ) will only be triggered HIGH at 7. Any combination can be selected if it satisfies this condition.


Old question but the CD4017 could also be used to trigger the CD4026 reset at 7.


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