# How to compare two numbers (nets, variables, constants) in Verilog

I am new to Verilog, and would like to learn how to compare two numbers. For example, let's compare a parameter or reg (say a) with the number 2 (2'b10). How this will be written in Verilog?

Equality and Relational Operators (return X if an operand has X or Z)

m == n  // is m equal to n? (1-bit True/False result)

m != n  // is m not equal to n? (1-bit True/False result)

m < n   // is m less than n? (1-bit True/False result)

m > n   // is m greater than n? (1-bit True/False result)

m <= n  // is m less than or equal to n? (1-bit True/False result)

m >= n  // is m greater than or equal to n? (1-bit True/False result)


Identity Operators (compare logic values 0, 1, X, and Z)

m === n // is m identical to n? (1-bit True/False results)

m !== n // is m not identical to n? (1-bit True/False result)


Example

If reg a is less than 2'b10, store 2'b11 in a.

if (a < 2'b10) begin
a = 2'b11;
end


Caveats

1. For most operations, the operands may be nets, variables, constants or function calls. Some operations are not legal on real (floating-point) values.
2. Operators which return a true/false result will return a 1-bit value where 1 represents true, 0 represents false, and X represents indeterminate
3. The === and !== operators are not supported for synthesis, because Z and X do not have the same meaning in simulation and hardware.
4. If you compare two numbers of unequal width, the smaller will be expanded. Unsigned operands are expanded by left-extending with zero. Signed operands are expanded by left-extending with the value of the mostsignificant bit (the sign bit).

Verilog numerical comparison operators are similar to those in C: ==, !=, <, >, <=, >=.