How is memory stored in a computer? Is it 1 bit per address so in order to get the value of an integer (32 bits) it must go through 32 addresses, get all the bits of 0's and 1's? I am a bit confused since I am reading a book on computer organization and architecture but the author does a poor job explaining thoroughly. Because what is really confusing me is when book uses examples and states 16 bit word of memory for an instruction. How is a word stored in memory? For this situation would it be 16 sequential addresses?

  • 3
    \$\begingroup\$ Step 1: Get a better book. Step 2: Google! \$\endgroup\$
    – John U
    Sep 26, 2013 at 8:37

1 Answer 1


99% of machines are byte addressable. A 16 bit word would occupy 2 addressable bytes. There are some unique machines where this is not the case, but for most RISC machines (especially the ones covered in an introductory computer architecture course) it's all byte addressable. Some architectures can address more than one byte at time (e.g. the memory data bus is not 8 bits), but the memory itself can be addressed at the byte level.

  • \$\begingroup\$ Quite a few microcontrollers, which is what I learned computer architecture on, do have bit addressable sections. The very common 8051 for example. \$\endgroup\$
    – Samuel
    Sep 26, 2013 at 2:39
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    \$\begingroup\$ Many current 32-bit CPU's have a 32 bit wide databus, allowing to retrieve 32 bits in parallel in a single clock cycle. Budget CPU's sometimes have 8 bit external databus, forcing them to fetch 8 bits in parallel at a time for four times in sequence \$\endgroup\$
    – jippie
    Sep 26, 2013 at 5:35
  • \$\begingroup\$ Yup almost all modern CPUs (I can't think of one that doesn't) have wider data busses, but the memory itself is byte addressable. E.g. the smallest unit of data you can address is a byte. @Samuel I didn't realize that the 8051 had bit addressable memory. Beyond the SFRs is this true? Kind of interesting. A sign of the times. Anyway I guess I assumed that when the OP wrote "computer" he meant a 32 bit RISC/MIPS like machine (which is the canonical machine in Paterson & Hennessy, which I sort of assume to be the de facto comp architecture book). \$\endgroup\$
    – Doov
    Sep 26, 2013 at 17:13

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