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I'm learning about pipelining but can't understand this abbreviation: "CL". You can see it in processors' schemes.
It is shown with with and without a line above it; what is the line for?
Diagram taken from here http://lgjohn.ecen.ceat.okstate.edu/4243/lectures/unpiped.pdf - page 3.
In the PDF file the text under the diagram is "With the clock wired as shown, the A and B data bus are driven from data read from the register file when CL is high, and the busses are driven from the ALU when CL is low".
Although not explicitly stated, I think the author intended CL to mean "CLock".
When the CLock is high the register file values are presented to the ALU input latches, and when the CLock subsequently becomes low the output from the ALU is presented to the buss and written to the register file by asserting W (Write)...which I suspect should have been marked on the diagram as bar-W.
I was going through some of the lecture slides and I have come to the conclusion that: CLK: Clock CL: Capacitor used with Crystal Oscillator
