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I have to write some data into an SPI EEPROM by the FPGA. FPGA will act as master, and EEPROM will act as a slave. The problem is as I do not have FPGA board as of now, I will be simulating these read write operations.

I am able to do some master side simulation, meaning I am able to see the commands going(MOSI), and clock etc, but on MISO how do I get data, as there is no slave simulation.

My question is how do I simulate the behavior of EEPROM, so that when I start simulation I will also get response from the EEPROM (in simulation).

My idea is I will put some known data in simulated EEPROM, and when the simulation starts I get data on MOSI and MISO both, and thus I can verfiy the working of read/write operations.

I am using Lattice FPGA and SPI EEPROM from Microchip.

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You can find simulation models for various EEPROM from the sites such as:

Free Memory Foundry or other similar sites. There you can find (for example) : "s25fl116k.vhd VHDL model of a 16-Mbit Flash Memory with 108-MHz SPI Multi I/O Bus." I am not sure if this is something you can use or not. But if you do a quick search on Google for your specific flash memory you will find it or something similar to it to use with your test code.

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