I have to write some data into an SPI EEPROM by the FPGA. FPGA will act as master, and EEPROM will act as a slave. The problem is as I do not have FPGA board as of now, I will be simulating these read write operations.
I am able to do some master side simulation, meaning I am able to see the commands going(MOSI), and clock etc, but on MISO how do I get data, as there is no slave simulation.
My question is how do I simulate the behavior of EEPROM, so that when I start simulation I will also get response from the EEPROM (in simulation).
My idea is I will put some known data in simulated EEPROM, and when the simulation starts I get data on MOSI and MISO both, and thus I can verfiy the working of read/write operations.
I am using Lattice FPGA and SPI EEPROM from Microchip.