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Hi while reading the datasheet for an ethernet controller chip, I came across the terms functional mode and test mode in relation to JTAG.

Can someone kindly explain these terms.

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Functional Mode: The inner logic is connected to the externally visible pins; the device works as it is intended to. If a sample/preload instruction is issued via JTAG, it is possible to sample the current pin states.

Test Mode: The inner logic is disconnected from the pins and pins are driven/read by the boundary scan logic only. This is usually referred to as EXTEST.

I find the explanations from XJTAG very user friendly, so you might want to check those out: http://www.xjtag.com/support-jtag/jtag-technical-guide.php

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