# IRF44n and push pull regulator topology

I'm studying the typical circuit implementations of push pull regulator topology. I have a question about it's off cycle. When the secondary get exited on the off cycle there is a back EMF also exited on the primary too , since the transformer is symmetric this is large as the primary current of the ON cycle.And because overall flux in the core is trying to depleted through the easiest path, so then there should be a huge current flown through that reverse diode ? Am I right here?

So the internal diode of the IRF44n would lead to flow massive amount of energy throug it. Isn't it? And get the device fry, or reduce the overall efficiency of the SMPS module?

Is that mean a circuit like this is a complete flaw?

• Think of this type of circuit as a regular transformer circuit and not as a fly-back where there would be an "off" cycle. – Andy aka Sep 30 '13 at 12:02
• so is it required to keep the duty cycle near 1 in this topology. The waveform have a state where both Q1 and Q2 are off. – Standard Sandun Sep 30 '13 at 12:31
• As far as I'm aware Q1 "charges" the primary and then Q2 "discharges" the primary then there is (or can be) a zero/neutral state. This means max duty cycle can be 50:50 for maximum power transfer or something less for controlling a smaller power. I believe (although I've not checked) that Q1 conducts and the moment it stops conducting Q2 conducts for the same length of time. – Andy aka Sep 30 '13 at 12:36
• which does mean Q1 Q2 cycles are not symmetric.If so the answer is acceptable. – Standard Sandun Sep 30 '13 at 12:41
• I've looked at the data sheet and it doesn't give details - I would expect Q1 to conduct for the same length of time as Q2 and that one conduction period immediately follows the other followed by a period of time that accounts for duty cycles less than maximum. If it's not like this then I can only assume that TR1 in your diagram is acting in some kind of partial fly-back mode. – Andy aka Sep 30 '13 at 12:50