I am trying to compile a design that consists of multiple files. There are library files with the primitives, than netlist files for the design, test vectors files used with the testbench and the test bench file itself. There are multiple cases that need to be tested and for this I may have to write a lot of testbenches and a lot of vector files in which only a couple of lines or so change. I think that it should be possible to use "pre-processor" directives in the verilog to simplify this task. Thus I write a batch file that has a list of vlog commands to compile everything. Within it I define some constant (like we do with #define in C language). Later in the verilog vector and testbench file I can use `if to find out if some part of the file should be compiled or excluded.
Now I have done this type of thing in C but not verilog. Can someone provide me with what steps and commands I need to use. Please note that I shall write a batch file with list of vlog commands and call it from within QuestaSim using the do command. This will compile all files that I need for simulation and also is expected to contain the "constant". Within the testbench I want that depending on value of someconstant "passed to it", different sections of the code in the file will be compiled. These different sections are enclosed in
ifdefendif This can be done in C using #ifdef, #endif, #ifndef, and #define pre-processor directives. Note that I am using QuestaSim which is similar to ModelSim, more like its big brother. I have never used this "pre-processor" feature of verilog before.
The problem is that, the batch file contains commands for questasim while the files being compiled contain verilog instructions for hardware description.
So the question is, how do I do this or is it even possible to do this?