Evaluate logical expression with a couple NAND gates

Question

I'm trying to implement a clever way to do error correction of 4 bits with the classic 3 parity bit correction and such.

I'm constrained by the number of logic gates I can use, but I'm trying to implement the following logic expression

OUT = AB(~C) + A(~B)C + (~A)BC + ABC

I have access to A, B, C, ~A, ~B, ~C, (A + B), (A + B + C), ~(AB), ~(BC) from other parts of the circuit. I also have exactly one inverters and 4 NAND gates (2 inputs per gate) to spare. Is it possible to implement the above logic function?

(I am using ~ as logical NOT)

I've messed around with De Morgan and Karnaugh maps but they don't help much when it comes to gate-specific constraints like these.

UPDATE: I've freed up 1 extra inverter and 1 extra NAND, for a total of 2 inverters and 5 NANDs.

Answer 1

I think this is a solution, after playing with the expression a bit.

^{simulate this circuit – Schematic created using CircuitLab}

Derivation:

$$ AB\overline{C} + A\overline{B}C + \overline{A}BC + ABC$$ $$ = AB(C+\overline{C}) + A\overline{B}C + \overline{A}BC $$ $$ = AB + A\overline{B}C + \overline{A}BC $$ $$ = AB + C\cdot(A\overline{B} + \overline{A}B) $$ $$ = \overline{\overline{AB} \cdot \overline{C\cdot (A\overline{B} + \overline{A}B)}} $$ $$ = \overline{\overline{AB} \cdot \overline{C\cdot (A+B)\cdot\overline{AB}}} $$ Turning the 3-input NAND into 2 2-input NANDs and an inverter: $$ = \overline{\overline{AB} \cdot \overline{C\cdot \overline{\overline{(A+B)\cdot\overline{AB}}}}} $$

Answer 2

Following up on @Dave Tweed, we can simplify the logical expression to

OUT = AB + BC + AC

Using DeMorgan's this again is equivalent to:

OUT = (AB)'' + (BC)'' + (AC)
OUT = ((AB)' (BC)')' + (AC)

This as it is, can easily be converted to a logic circuit that uses 2-input NAND gates

^{simulate this circuit – Schematic created using CircuitLab}