I'm trying to implement a clever way to do error correction of 4 bits with the classic 3 parity bit correction and such.
I'm constrained by the number of logic gates I can use, but I'm trying to implement the following logic expression
OUT = AB(~C) + A(~B)C + (~A)BC + ABC
I have access to A, B, C, ~A, ~B, ~C, (A + B), (A + B + C), ~(AB), ~(BC) from other parts of the circuit. I also have exactly one inverters and 4 NAND gates (2 inputs per gate) to spare. Is it possible to implement the above logic function?
(I am using ~ as logical NOT)
I've messed around with De Morgan and Karnaugh maps but they don't help much when it comes to gate-specific constraints like these.
UPDATE: I've freed up 1 extra inverter and 1 extra NAND, for a total of 2 inverters and 5 NANDs.