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When designing ASICs, engineers may use a wide set of architectural and micro-architectural tools and approaches for management of power consumption of the chip:

  • Retention registers - registers which have a separate power line and store data while the circuit is not powered
  • Power domain separations - allows for separation of the circuit into distinct power domains which may be powered off independently of each other
  • Clock domain separation - allows for separation of the circuit into distinct clock domains with clock frequencies tailored for the required performance and power consumption.
  • Dynamic voltage scaling - allows for reduction of supply voltage when the chip is in "low load" mode.
  • Dynamic frequency scaling - allows for reduction of clock frequency when the chip is in "low load" mode.
  • Dynamic clock gating
  • Few more

I know that there are FPGAs with clock gating capabilities, and I remember that I read once about FPGA which has retention registers, but are these the only ones?

My general question is: what HW power management capabilities are present in the state of the art FPGAs today? I'm not seeking for explanations of the techniques (though good references are welcome), but just want to be updated on the latest FPGA features.

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  • \$\begingroup\$ 2 downvotes without any comment? Guys, I can't get enough information from them in order to improve the question. \$\endgroup\$ – Vasiliy Oct 2 '13 at 13:38
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    \$\begingroup\$ The question is very broad. What specifically is your question - is it only general interest, do you have an application you are working on, is it for school? \$\endgroup\$ – user36129 Oct 2 '13 at 13:50
  • \$\begingroup\$ @user26129, this question can't be very broad - even in ASICs there are not too mamy techniques for power management (the ones that I listed + few more). I'm interested for my own education as a professional in the field of microelectronics who has very minor experience with FPGAs. \$\endgroup\$ – Vasiliy Oct 2 '13 at 14:31
  • \$\begingroup\$ You might be better off asking a Xilinx/Altera/Lattice/Microsemi FAE for more information. \$\endgroup\$ – dext0rb Oct 2 '13 at 15:20
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    \$\begingroup\$ @user26129, I believe that you could just list all these techniques you have in mind in an answer. This could be more productive than explaining to me what little I know about power management, and, probably, shorter. I'm not interested in SW aspects, just architectural/micro-architectual HW approaches. Thx \$\endgroup\$ – Vasiliy Oct 3 '13 at 17:29
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First let me say that power is not an FPGA strong point. However, there are some things that can be done to tame that power hog (some overlap what you have listed for asics, some are vendor/model specific):

  • Clock domain separation (same as in asics). Use slower clocks whenever you can.
  • Clock gating. This the traditional way of 'disabling' blocks of circuitry.
  • Separation into Banks. FPGAs usually have multiple banks, and what you can safely power down varies with vendor and model, but they can have separate power supplies for IO, high speed transceivers, differential clock inputs, among others.
  • Programmable output slew rate and drive strengths.
  • Power-down option for certain built-in hardware blocks (such as memory blocks, hardcopy blocks, certain PLLs, specialty transceivers, etc.).
  • Partial Reconfiguration, which is being able to reconfigure part of the FPGA (with other parts of it being operational). When certain features/modules are not needed, you could "erase" them for minimal power, and reconfigure them later on, or even reconfigure the FPGA with a lower-power design/profile.

There is some additional information on Altera's Reducing Power Consumption and Increasing Bandwidth on 28-nm FPGAs

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  • \$\begingroup\$ Did you mean Clock Domain separation in bullet #1? Can you elaborate a bit on bullet #4 (programmable drive strength)? \$\endgroup\$ – Vasiliy Oct 8 '13 at 16:00
  • \$\begingroup\$ @vasily Output (pin) slew rate and drive strength may help reduce power consumption mainly because of resistive losses due to the squared relationship: p=(i^2)r. Half the current for twice the time consumes half the energy (to charge the same capacitive load). I think decreased reflections will also help, but I'm not sure if significantly. \$\endgroup\$ – apalopohapa Oct 8 '13 at 17:05
  • \$\begingroup\$ Thanks, I'll search for more info on these topics on the web. \$\endgroup\$ – Vasiliy Oct 8 '13 at 17:19

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