Usually in digital design, we deal with flip-flops that are triggered on a 0-to-1 clock signal transition (positive-edge triggered) as opposed to on a 1-to-0 transition (negative-edge triggered). I have been aware of this convention since my first studies on sequential circuits, but have not questioned it until now.

Is the choice between positive-edge triggered and negative-edge triggered arbitrary? Or is there a practical reason why positive-edge triggered flip-flops have become dominant?

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    \$\begingroup\$ The way most of these kind of things happen is someone does it one way, someone else needs to make hardware compatible, and does the same, and a few years later you have a an accidental standard. \$\endgroup\$ Commented Oct 3, 2013 at 9:32
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    \$\begingroup\$ I work with Flip-flops which are mostly Falling Edge triggered. I had exactly opposite question! \$\endgroup\$
    – Swanand
    Commented Oct 3, 2013 at 10:06

3 Answers 3


Best guess: the positive-edge trend is a byproduct of designs trying to use a little area/parts as possible before the 1970's. A cost saving measure for production by increase the number of chip per wafer. Modern pos/neg-edge DFFs often have equal total area, therefore the positive-edge trend is now legacy practice.

Area saving came form "Classical" D-flip-flop designs. The modern master/slave components of a D-flip-flop can use two 5-transistor latches; Patents WO1984003806 A1 and US4484087 A both filed on Mar 23, 1984. An 8-transitor D-latch was patent was filed Feb 6, 1970; US3641511 A. For the sake of simplicity designs based on SR/SnRn latches will be be refereed to as "Classical" and "Modern" for designs using mentioned D-latch/S-cell patents.

In a IC design, a NAND gate uses less area then NOR gate because of characteristic properties of a NMOS and PMOS. Form there, the area saving size trend cascades. D-latches form SnRn latches are smaller then from SR latches. The Classical D-flip-flop designs are based on these logic gates. After searching for several designs Classical positive-edge designs are always smaller then Classical negative-edge designs. Migration to the Modern happened as the as the chips cost became favorable: area savings vs royalty fee.

Digging a little deeper to demonstrate area differences:

Classical positive-edge D-flip-flop: Schematic based Wikipedia's Classical positive-edge-triggered D flip-flop description and diagram using five NAND2 and one NAND3. This uses a total of thirteen NMOS and thirteen PMOS.


simulate this circuit – Schematic created using CircuitLab

The best Classical negative-edge D-flip-flop I could find is uses two D-Latches and two inverters. Schematic referenced form http://students.cs.byu.edu/~cs124ta/labs/L02-FSM/HowToUseMasterSlave.html. This uses a total of eighteen NMOS and eighteen PMOS. Placing an inverter on the classical posedge above will lower the transistor count of this design. Either case, the classical negative-edge is bigger then positive-edge design.


simulate this circuit

A Modern D-flip-flop design can look the following based on patents WO1984003806 A1 and US4484087 A five transistor D-latch description. This uses a total of five NMOS and five PMOS; big area savings compared to Classical. Reversing the master/slave order would create a negative-edge flip-flop of equal size.


simulate this circuit

I am only demonstrating the smallest possible designs. Designs can very based on design requirements, allowed standard cell libraries, reset/preset features, or other reasons.

  • \$\begingroup\$ That's a good point. I was approaching the problem from the clock distribution, but I can see how DFF architecture could be different. However, I think negative edge triggered flops can have an NAND-based architecture too. Can you add a schematic of the architecture(s) you are talking about? \$\endgroup\$ Commented Oct 4, 2013 at 1:16
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    \$\begingroup\$ @trav1s, I updated my answer with examples and some patent research. \$\endgroup\$
    – Greg
    Commented Oct 4, 2013 at 21:41
  • \$\begingroup\$ I wonder to what extent chips use other techniques for latches which need to operate based upon edges of an externally-applied clock? For example, using two-phase clocking and semi-dynamic logic one could reduce the required number of transistors per flop to seven [a fully dynamic approach would be six, but adding a seventh transistor allows one to add a fully static "hold" state]. \$\endgroup\$
    – supercat
    Commented Oct 4, 2013 at 23:14
  • \$\begingroup\$ @Greg, great work. Your finding is just about what I expected. That 10T transistor at the end is a beautiful thing. \$\endgroup\$ Commented Oct 5, 2013 at 0:12
  • \$\begingroup\$ Interesting answer and very insightful. You are saying that posedge trend came before 70's, but this is not consistent with my findings (see my answer). What made you come up with this date? Just a guess, or do you have some additional info? If it is the latter, I'll be glad to get a reference (in order to improve my own answer :)) \$\endgroup\$
    – Vasiliy
    Commented Oct 5, 2013 at 1:45

There are some base assumptions here that was covered in another post (which I can't find now).

If you count the total number of placed logic elements and clocked logic (total number of FF's shipped) they are probably going to be in processor and microprocessors, Intel, DEC etc. The manifestation of this is that you end up with a small groups of people/teams who are responsible for designs covering many decades, with not a lot of details of the internal workings.

Conversely you have many different teams working on ASIC flows, with many more projects but corresponding less volume.

Most processor designs are actually not positive or negative edge clocked but are designed using a double latch, NOC (Non Overlapped Clock) complimentary clocking scheme.

So you end up with a inputs -> (logic cloud) -> latch from clock -> logic cloud -> latch from !clock scheme. Which is the canonical form of a master slave FF with logic stuffed inside.

This sort of design methodology has several advantages but also has additional complexity.

Another unfortunate thing is that this design methodology is not taught in most universities. All of the Intel x86 designs are of this sort (one must not confuse external operation of interfaces with internal operation) with the notable synthesizable SOC cores that they have been designing for mobile handsets.

An excellent discourse on this can be found in "Dally, William J., and John W. Poulton". Digital Systems Engineering. Cambridge University Press, 1998. section 9.5 discusses "open loop synchronous timing" <-chapter title. But to quote "Edge-triggered timing, however, is rarely used in high-end microprocessors and systems designs largely because it results in a minimum cycle time dependant on clock skew".

Yes, a totally pedantic answer. but an important methodology that is little known, considering how many total transistors are out there in these designs (lots and lots).

  • \$\begingroup\$ I read this three times, but I still can't see how is this related to OP's question... \$\endgroup\$
    – Vasiliy
    Commented Oct 5, 2013 at 12:06
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    \$\begingroup\$ Also, saying that CPUs are built from latches only is a bit of exaggeration (maybe even not a "bit of"). Latches are used in high performance critical logic (mainly data paths), but there are still many flip-flops present. The main disadvantage of latches is timing analysis difficulty - due to "time borrowing" capability of latch based design (the same capability which makes this design "faster"), it is very difficult to test latch based design for timing closure. In non-critical parts of CPUs mainly FFs are used. \$\endgroup\$
    – Vasiliy
    Commented Oct 5, 2013 at 12:15
  • \$\begingroup\$ Key word in the title is "usually" - 1) in the total # of different types of chips designed - then ASIC flow and edge trigger will be usual. 2) if total # of shipped logic element/transistors CPU designs win and then latch based double clock wins and then the statement is invalid. \$\endgroup\$ Commented Oct 5, 2013 at 14:56
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    \$\begingroup\$ You can't look at the interface of these chips to determine what the internal operation is. As I stated a Master slave Flip Flop is just a simplified versions of a two phase clock double logic cloud latch based design. Timing analysis is not difficult, in fact it's simplified. You just better be certain of your clock domains. \$\endgroup\$ Commented Oct 5, 2013 at 15:01
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    \$\begingroup\$ No, key words are "flip-flop" and "edge of the clock". Latches are level sensitive devices not edge sensitive. Apples and oranges man - if I want to know why are oranges orange, the fact that there are many people who prefer apples is completely irrelevant. \$\endgroup\$
    – Vasiliy
    Commented Oct 5, 2013 at 15:08

Current CMOS technology's performance (in terms of power/area/speed/cost) seem to be insensitive to the triggering scheme used.

I can't prove the above statement rigorously because it requires a lot of preliminary knowledge and research, and even the summary of the proof will probably be too long for an answer. To my best knowledge there are no differences, therefore let me just assume that this is the case.

I either don't know if your statement about flip-flops being usually triggered on the positive edge of the clock is correct (I believe it is). Let me assume that this is also correct for the purpose of the following discussion.

Under all the above assumptions I see just two possibilities:

  • Positive edge triggering became a standard because it had some clear advantages at some time in the past. After the technology which exploited this advantage became outdated, positive edge triggering still remained the facto standard.
  • Positive edge triggering became a standard without any engineering legitimacy, i.e. it did not provide any advantages in any logical family and any technology node in the past.

In order to see when did positive edge triggering became a standard, I decided to follow the evolution of Intel's CPUs clocking schemes:

  1. 4004: Used two phase externally supplied clock. It seems that latching of Data Out was done on negative edge of \$\phi _2\$.
  2. 8086: Latching of Data Out was done on negative edge of CLK.
  3. 80386: Used positive edge of CLK2.
  4. 80486: Used positive edge of CLK.
  5. Pentium: Used positive edge of CLK...

It seems that Intel started with negative edge triggering (if this term may be applied at all to the very first CPUs), but switched to positive edge triggering starting with 386.

8086 used HMOS technology (some kind of Depletion-load NMOS logic) whereas 80386 was CHMOS (it is a kind of CMOS). Looks like the adoption of positive edge triggering happened in parallel with the adoption of CMOS technology. We assumed that CMOS does not provide any any advantage to positive edge triggering, therefore it seems that this convention is arbitrary.

However, we must keep in mind three points:

  • We assumed that current CMOS technologies do not provide any advantage.
  • The above assumption was not proven or debated in any form.
  • From datasheets it is clear on what edge Data Out is latched, however this may not represent the internal implementation.

Clearly, there is room for additional research. To be continued...


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