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Lately I have been working on a new design in Altium (a derivative of my last ARM board) but I have run into a problem. I am at the stage of compiling the schematic documents and checking for discrepancies before making the PCB document and routing.

I am getting the error where the the identifiers of schematic ports do not match up with the corresponding port. I can seem to find a way to globally reset the identifier values inside the properties of each port. Does anyone know how to do this?

At my job this past summer we used ports in lieu of net labels it may be bad practice but it worked flawlessly with the designs we did at work. I've spent a while searching for an answer online as well as manually searching the Atlium menus but have not found a solution, if anyone knows I'd appreciate it, if I should just redo the whole thing with netlabels then I'd like to know about that to.

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If you're using ports, you need to (well, really, really, really should) have an upper-level schematic that has all your schematics as sheet entities, and defines the interconnections between each sub-sheet.

Anyways, it sounds like you're looking for the "Synchronize Sheet Entries and Ports" menu option:
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You can also update each schematic symbol individually by right-clicking on the schematic symbol on the top-level document, and selecting "Synchronize Sheet Entries and Ports" in the menu.

I'm not entirely sure if this answers what you're asking, as you're describing it in a way I haven't heard before. If you can post the exact content of the project compilation errors, I can probably be more specific.


If you're using schematic ports to connect separate schematics without a upper-level schematic containing each sub-sheet as a schematic symbol and wires to dictate symbol interconnectivity, well... you're doing it wrong. You should be using off-sheet connectors for that (but that's a terrible way to define inter-sheet connectivity anyways).


Edit:

From the OP's comments below, it sounds like the issue is the error checker is complaining that if you have multiple schematic pages with ports specified as "output", that are connected together, this will produce an error. While this error can be very useful, there are many situations where you do want to connect multiple outputs together (Think of multiple SPI slaves. The outputs are tri-stated until CS is asserted).

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The generation of interconnection errors are generated by the settings on the "Connection Matrix" page of the "Project Options" dialog. You look for the box at the intersections of the two pin or port types you want to modify the reporting for, and then clicking the box cycles through the possible error or warning generation options.

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  • \$\begingroup\$ Thanks for your answer! I found a solution by just frantically trying different things. What I cam up with was make all the ports match up with the directionality of the components either input, output, or bidrectional. An easy hack that I am sure is bad practice on all counts is to make all the ports bidirectional, the compiler reports no connection errors after that. Since I don't plan on doing any simulation I think I can get by with this. When I was working on my senior thesis I did everything the right way with a top level sheet but I still have tons of errors, using ports fixes it. \$\endgroup\$ – Adam Vadala-Roth Oct 4 '13 at 23:33
  • \$\begingroup\$ @AdamVadala-Roth - So you have issues with the compiler complaining about multiple output ports connected together? Why don't you turn that warning off? \$\endgroup\$ – Connor Wolf Oct 5 '13 at 0:11
  • \$\begingroup\$ See new edit for how to tweak the warnings. \$\endgroup\$ – Connor Wolf Oct 5 '13 at 0:20
  • \$\begingroup\$ I guess I could turn off the warning, but I found that if I either set all the ports as bidirectional or matched up their directionality with the parts of the circuit they are interconnecting it solved all the compiler errors. Thanks for everyone's response, I hope this post and comments helps others in the future! \$\endgroup\$ – Adam Vadala-Roth Oct 10 '13 at 22:33

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