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A register is a temporary storage facility within the CPU that holds data for computation purposes.

What I question is how this is structured via engineering principles within the circuity:

1.I had first thought that all information held electrostatically was implemented in capacitors. Am I right or am I wrong within the context of CPU data storage?

2.I also had thought that maybe a logic gate can loop data until appropriate action/machine code changed the flow of logic/data within the circuit to take appropriate action from memory. Yes?

3.Last I can think is that the data enters the CPU from RAM in correct format, is parsed by the CPU's microsequencing circuity, and enters an electrolytic capacitor within a motor capacitor.

Do I have it right, or please correct me.

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    \$\begingroup\$ Point 3 made me smile - please explain how you go from microsequencing circuitry to a motor capacitor like that (or maybe you intended to put a smile on someone's face)? Possible troll alert? \$\endgroup\$ – Andy aka Oct 5 '13 at 21:50
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Option 2. Here is the most basic gate-based semiconductor memory, the R-S flip flop:

R-S flip flop

When either R or S is triggered, the feedback loop causes the system to maintain its state until the other input is triggered. As such, it is capable of storing a single bit. Static memories (of which registers are just small slices of) are composed of arrays of thousands to millions of similar circuits.

Dynamic memories, OTOH, do use capacitors to store bits. Since the capacitors are very leaky they must be refreshed very often, and this leads to higher power consumption and lower access speeds than with static memories. This is balanced by much higher density, since the circuitry is much simpler.

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  • \$\begingroup\$ So I was right? Also, what purpose would capacitors serve within a CPU? \$\endgroup\$ – Barium Microsequencer Oct 5 '13 at 21:46
  • \$\begingroup\$ Number 2 is correct, in the context of registers. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 5 '13 at 21:47
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    \$\begingroup\$ Small note: Usually D-triggers are used for storing data in registers. \$\endgroup\$ – johnfound Oct 5 '13 at 21:48
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Historically, some processors have used transistor gate capacitance as a means of storing information because it reduces the number of transistors required to hold each bit. A RAM with separate read and write ports would require three active transistors (one of which should have a large gate) and no pull-up devices per bit. By comparison, a RAM which didn't rely upon gate capacitance would generally require four active transistors and two pull-up devices per bit. Note that the style of RAM described here is very different from that used in dynamic memory chips, which rely upon drain capacitance and require special protocols when reading and writing. The style of RAM described here can be read and written in any desired pattern, subject only to a requirement that no bit ever goes very long without having been written.

Dynamic logic had significant advantages when used in PMOS or NMOS chips (which only use one kind of transistor). Pull-up devices were expensive and wasted power, and while a transistor might have needed a larger-than-normal gate to ensure it could remember things as long as it needed to, a dynamic bit which used two normal-sized transistors and one quad-sized transistor would still be more efficient than a "static" bit which needed four active transistors and two pull-ups. Improvements in chip manufacturing, however, have greatly reduced the advantages of dynamic logic. CMOS devices' ability to use interconnected PMOS and NMOS transistors greatly reduces the expense formerly associated with the passive pull-ups. The shrinking scale of chips has increased the relative cost of "deliberate" gate capacitance (e.g. even "capacitor-gate" transistor that can hold information for 10us would only have to be 1/100 as big today as in 1976, it would still be hundreds or thousands of times larger than the transistors needed to build a bit of static RAM). Thus, processor registers today are more likely to be constructed entirely out of static logic without any deliberate capacitance.

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