I am trying to get a MOSFET/IGBT driver to work for almost a year. The last efforts utilizing a bipolar Totem pole driver failed without mercy.

For some time I studied alternatives and came to AC coupled gate drive by Laszlo Balogh. (edit: see p.28 in this TI app note for more discussion. )

Now several difficulties made their way. But wait, first the schematic: AC coupled gate drive circuit following Laszlo Balogh


  • \$I_{load,max} = 200A \$ => 50A per n-ch-MOSFET IRF1405Z (4 in parallel),
  • \$V_{drive} = 6.4V \$ (it's for speed reasons, otherwise so far the resulting speed was way too high),
  • \$ V_{drain-source,OFF-state} = 6.4V \$,
  • Clamp circuit (TVS/Transient voltage suppression) diode omitted (because I only have individual ones and I fear blowing another set of MOSFET with this driver too),
  • frequency \$f := 5 kHz\$.
  • added after Nick's gentle post below: \$\tau = .001s\$ (even though I'm not sure if it is way too small for a frequency of 5 kHz -- I remember Laszlo using 100kHz and using \$\tau = .0001s\$)

Calculations (it's the first gate drive design where I involve severe mathematics - as I saw so far the alternative is destroying the switches):

  • Minimum coupling capacitor: \$ C_{CC} = 3uF\$,
  • \$R_{GS} = 463 Ohm\$,
  • Power,Driver bypass capacitor value \$C_{DRV} = 5uF\$,
  • \$R_{Gate,individual-MOSFET-unbalance-prevention} = 10 Ohm\$.


  • The voltage clamp was omitted due to simplicity, hopefully reliability (as I think diodes are the weak point here with the electrolytic capacitor) and the low drive voltage level (Vgs = 6.4). Otherwise the bias would result in not enough above the threshold voltage for turn on of the MOSFET. I hope the omitted voltage clamp is no problem at the low gate drive voltage.

  • Furthermore I calculated a very high \$ dV/dt = 100 million V/s \$ that results in a very low maximum pull down resistor of \$R_{GS,max} = 16 Ohms\$ ... (nevertheless I settled on 463 Ohms, the problem now is that this maximum \$R_{GS}\$ voltage condition is not met!) Do you have a better idea to calculate dV/dt instead of \$ dV/dt = \frac{ V_{th} }{ C_{GateDrain,0V} \cdot dV_{inrush}/dt } = R_{internal,mosfet} + R_{gate} + R_{low,driver} \$?

Potential solutions:

  • In the mentioned AN the dV/dt rating was stated as crucial for safe power up. dV/dt limit depends on gate resistance and other resistances as to my understanding so far. Now that we don't have a gate resistor here for the AC coupled gate driver the dV/dt limit is fairly giant (see specifications above). During power up the Rgs has the crucial task to keep the MOSFET off, therefore we have to keep the value low as the voltage drop across Rgs must be lower than Vthreshold. The current flowing through Rgs during start up is proportional to dV/dt inrush. And here we have the problem. Is \$dV_{limit}/dt \neq dV_{inrush}/dt\$? That would solve our issues as currently I use dV/dt upper limit for self-induced turn-on for calculating the \$R_{GS,max} = 16\Omega\$.

Rgs trade-off:

  • A problem mentioned in answers below and additions above was the resulting \$R_{GS}\$ being low. So I should mention Laszlo's explanation that it's a trade off between high switching frequency (\$\tau = small \Rightarrow R_{GS} = small\$) and power loss (because of the wasted current that flows through RGS the more the lower its value).)

Parallel MOSFETs:

  • Do you think driving parallel devices could be dared despite the additional resistors required for protection of self-oscillation (properly heat-sinked and balanced inductances of course)?

Benefits of freely choosing \tau higher than required?

  • Now the question is if there are any benefits of choosing \$\tau \gt \tau_{min}\$ freely higher than the minimal value required for getting a positive capacitor value? It is tied to frequency and duty cycle - that generate a lower limit for it - as well as to capacitor value and resistance: \$\tau = R_{GS} \cdot C_{CC}\$. In the AN the correct value is picked per desire. Obviously if we increase \$\tau\$ then either Rgs or Ccoupling have to be decreased.

Are there benefits of increasing Tau other than flexibility in the Rgs and Ccoupling?

Alternatives & limitations:

  • Thank you for pointing out, I'm open to suggestions of alternatives. I just don't want to use ready gate drive ICs because I feel they are not as easy adaptable to other MOSFETs/IGBTs and because they need extra circuitry anyway.
  • Of course a drawback of this gate driver (AC coupled) is that it's not capable to drive a high side switch if I'm not wrong. Using bootstrap or an additional drive transformer could solve it -- but complexity will rise. (see Laszlo Balogh's Application Note again - look for Transformer coupled gate driver)

PWM driver module used

  • I use STM 32bit development board for control - it has several PWM outputs, those I use regularly - unfortunately under high losses due to not enough protection of the inputs? Another mystery I try to figure out. The GPIOs handle 1 A of current if I remember it correctly. (I wonder if voltage spikes will reach the inputs via a capacitor in AC coupling?)
  • Nick pointed out, that the signal amplitude (3.3V) of the STM 32bit \$\mu Controller\$'s outputs will be way too low for driving the non-logic-level MOSFET directly. I forgot a capacitor can't be charged to a higher voltage than the supplying voltage! => I either add a scaling transformer or buy a IR2121 or the MIC4426 1.5A driver as proposed by Nick Alexeev.

  • Is it possible to add a logic level transistor inbewteen an external +6.4V power supply and the coupling capacitor alternatively to the scaling transformer?

    • Or is a voltage booster a viable solution? Or better stick to a separate driver module now that part count advantages are relativized?
  • 1
    \$\begingroup\$ What gate drive IC or PWM controller are you using? You still have to provide sufficient gate drive current (obviously). I must admit that your problems don't seem too clear to me at the moment. I should read it a few more times. Why did you choose this AC-coupled gate driving scheme? At the moment, I'm not convinced that AC-coupled gate is the right scheme for your situation. \$\endgroup\$ Oct 6, 2013 at 3:24
  • \$\begingroup\$ Hi Nick, I'm not sure too - I read Laszlo's High speed switching Application Note several times and found the AC coupled driver to convince me. (I added a sentence about it - about the PWM controller too.) I'm sure I just wrote too confusing, luckily our community is splendid and edited my post and mistakes right away. :) \$\endgroup\$ Oct 6, 2013 at 20:52

2 Answers 2


I'm going to start with conclusions and then follow up with some reasoning. Hopefully will be helpful.

  • 6.4V will be really marginal \$V_{\text{GS}}\$ for this FET (IRF1405Z). Since the Miller Plateau (Fig 6) occurs at about that voltage, it may not switch fully at these currents. If you can't get about 10V to drive the FET, then you should find a low \$V_{\text{th}}\$ FET to use instead.
  • A direct coupled gate drive should be used instead of and AC coupled drive. The application doesn't seem to need an AC drive. And an AC drive will result in lower \$V_{\text{GS}}\$ than even 6.4V.
  • There is a big difference between values needed for passive pull down \$R_{\text{GS}}\$ during the slow system start-up dV/dt, and total gate circuit resistance \$R_g\$ for switching operation. \$R_{\text{GS}}\$ can be very high value, like 10KOhms to 100KOhms for the slow (usually milli-sec) start up dV/dt. Total gate resistance \$R_g\$ will typically need to be less than ~200 Ohms for high dV/dt switching. For more about this you should look at this answer which I think explains it all (Yes, I'm biased).
  • Because of the voltages involved in this case, only 6.4V, dV/dt isn't really an issue here. If there is really only 6.4V \$V_{\text{ds}}\$, then it won't be possible for dV/dt to drive \$V_{\text{gs}}\$ up to \$V_{\text{th}}\$ of the IRF1405Z.

AC Coupled Gate Drives -- What are they good for?

The only reason to use a capacitively coupled gate drive is if for some reason a negative voltage is needed on the FET gate when the FET is turned off. A problem with the AC drive is that an amount of positive gate voltage is always lost from the input drive levels, and it will be a variable amount depending on the duty cycle of the drive waveform or the clamping voltage.

In this case where the clamp circuit has been removed the peak \$V_{\text{GS}}\$ is a function of duty cycle (DC) as well as source value. The drive signal on the FET side of the coupling capacitor (\$C_c\$) will be normalized to the average value by the passive pull down \$R_{\text{GS}}\$ and would be equal to \$\text{(1-DC)} V_{\text{DRV}}\$. For example with 6.4V \$V_{\text{DRV}}\$, if the switch duty cycle is 50% then the high state \$V_{\text{GS}}\$ would be 3.2V. If duty cycle were 20% the high state \$V_{\text{GS}}\$ would be 5.1V.

Looking at Figure 1 of the IRF1405Z datasheet, \$V_{\text{GS}}\$ of 5.1V results in max drain current of 40 Amps, or not fully on. This would cause the FETs to over dissipate and burn out. With the high currents that will be switched, you can't afford to have low gate voltages for any reason.


The IRF1405Z has 12nH of package inductance in the drain and source connections, and a \$C_{\text{oss}}\$ of ~1000pF at 12V \$V_{\text{ds}}\$. That should limit the \$V_{\text{ds}}\$ rise time for the die to about 10 nsec. Figuring a high Q resonant response for the LC and steady state off voltage for \$V_{\text{ds}}\$ of 6.4V, \$V_{\text{ds}}\$ at the die could ring to 12.8V. That's a dV/dt of about 1V/nsec. Using the equation, from the answer cited earlier, for \$V_{\text{gs}}\$ under dV/dt:

\$V_{\text{gs}}\$ = \$C_{\text{gd}} V_{\text{dsSlp}} R_g \left(1-e^{-\frac{t}{R_g \left(C_{\text{gd}}+C_{\text{gs}}\right)}}\right)\$

And putting in values for IRF1405Z:

\$V_{\text{gs}}\$ = \$\text{(500pF)} \text{(12V/10nsec)} \text{Rg } \left(1-e^{-\frac{\text{10 nsec}}{\text{(500pF + 4500pF)} \text{Rg}}}\right)\$

It is possible to see that any value for \$R_g\$ is going to leave \$V_{\text{gs}}\$ less than about 1V. So, it looks like dV/dt isn't going to be an issue. (Never thought I'd say that!)

  • \$\begingroup\$ And hey I already found your solution before. Once I reach the 15 reputation for upvotes, i will join the efforts there. Oh, I'm biased now too? What makes me crazy is that the \$V_{GS}\$ limits the charging current too much if it is chosen too high. I will need some time to fully take my lessons out of your detailed and plenty effort (like Nick's)! After implementing the changes I will come back and post a hopefully found solution. Btw a direct drive would imply using a logic level (=> low Vthreshold) MOSFET/IGBT. As I don't have any I will have to find a solution. \$\endgroup\$ Oct 17, 2013 at 1:13
  • \$\begingroup\$ Accepted your answer as neither Nick nor anyone else seems to bother to upvote your detailed answer and I fixed parts of Nick's answer myself which showed that the results of his calculations - apart from the factor 4 of Q as it is 4 FETs - are in line with mine. Your answer is very detailed + in combination with your linked dV_ds / dt answer (L3 model of a MOSFET) is allowing me to create a working DIY driver. Thank you. Yours faerietree \$\endgroup\$ Apr 6, 2017 at 17:23

RGS = 463Ω in the O.P. is a surprisingly low resistance.
I did the calculation from that TI app note: the equations on pp. 36-38.

\$ Q_G = 4 \cdot 260 \$ nC. The number 260nC comes from the IRF1405 datasheet.
\$\tau = 0.1\$ sec. Let's assume this value.
\$f_{DRV} = 5 \$ kHz. As in the O.P.
\$V_{DRV} = 6.4 \$ V. Also as in the O.P.


\$C_{C,min}= \cfrac{20 \cdot Q_G \tau f_{DRV}}{V_{DRV} (2\tau f_{DRV}-5)}\$

Since the switching frequency is relatively high, \$\cfrac{\tau f_{DRV}}{2\tau f_{DRV}-5} \approx \cfrac 1 2\$, and the equation for \$C_{C,min}\$ simplifies.

\$C_{C,min} \approx \cfrac{10 \cdot Q_G}{V_{DRV}} = 1.625\$ μF

\$R_{GS} = \cfrac{\tau}{C_C} = \cfrac{0.1}{1.625 \cdot 10^{-6}} = 61.5\$ kΩ

I don't know if this is the root cause of the O.P.'s woes, but I've got a value for RGS, which is 2 orders of magnitude different from the one in the O.P.

O.P.'s note: Thank you, if we take O.P.'s value for \$\tau = 0.001 s\$ that was initially forgotten to be specified, we get a \$R_{GS} = 615 \Omega\$ which is in the area of the O.P.'s result - it's a trade off between high switching frequency (\$\tau = small \Rightarrow R_{GS} = small\$) and power loss (because of the wasted current that flows through \$R_{GS}\$ the more the lower its value).)

N.A. in response to updates in the O.P.: Regarding the last paragraph in the O.P. about PWM driver. I have doubts.

  1. Earlier, you wrote that \$V_{drive} = 6.4\$. STM32 runs off +3.3V. Its GPIO can't put out 6.4V.
  2. I don't know of a μC (microcontroller) whose GPIO can source or sink 1 A (one Ampere). Even if it's a peak load, 1 A is a lot of current for GPIO. I suspect that your design is missing a proper gate driver. Here's an example among many gate driver ICs.
  • \$\begingroup\$ Thank you Nick, it's so good to see your recalculation! I should add mine to the thread. Such high values also happened to me, but they fall extremely quick with decreasing \$\tau\$ by one magnitude (I used \$\tau = .001 s \$). Now I realised you accidentally took \$\tau = 1s\$ instead of your mentioned .1 seconds and corrected it accordingly so that instead of \$R_{GS} = 615\$ kΩ a value of 61.5 kΩ results. I calculated the R_GS following your calculations using my Tau \$\tau = .001s\$ and came to 615Ω then. A low value should not be a prob, L.Balogh himself got 400 Ω in an example. Woe:f,Tau \$\endgroup\$ Oct 6, 2013 at 21:42
  • \$\begingroup\$ Good you pointed out that the charge has to be multiplied by 4! Thank you! \$\endgroup\$ Oct 6, 2013 at 23:43
  • \$\begingroup\$ Another remark: Either you or me use the wrong datasheet, I used: IRF1405 Z PbF with 75Amps -- do you think the current rating is not high enough? I added yet another remark to the Rgs dilemma (as we have an upper limit for it of 16 Ohms). Apparently we both are above it, leading to failure at power up. \$\endgroup\$ Oct 7, 2013 at 0:30
  • \$\begingroup\$ @jonardaron gate drive resistance for \$\frac{\text{dV}}{\text{dt}}\$ is all the resistance in the gate circuit as seen from the gate of the FET, it is not just the \$R_{\text{GS}}\$ passive pulldown, but also includes gate drive output and should be much lower than just the passive pulldown resistor. \$\endgroup\$
    – gsills
    Oct 7, 2013 at 5:39
  • 1
    \$\begingroup\$ @jonardaron There is a difference between the passive pull down \$R_{\text{GS}}\$ needed for the slow dV/dt at system start up and the total gate circuit resistance needed for switching operation of the FET. I think Nicks' answer and conclusion are really good. I am going to put up an answer to try and clear up some misconceptions that linger. \$\endgroup\$
    – gsills
    Oct 9, 2013 at 22:04

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