There are two main "types" of power consumption:
Static: the power consumed while the device is on but doing nothing. The proportion of static power in the total power generally increases as technology dimensions shrink. In 90 nm and below it is a significant portion that must be factored into the power budget.
Dynamic: the power consumed while the gates inside of the device (including I/Os) change state (i.e., got from 0 to 1 or 1 to 0). That's why the operating frequency and functionality increases the accuracy of the estimate.
Xilinx has two tools for estimating power:
- An excel sheet, as pointed by Brian Carlton.
- A binary called 'xpwr' (part of ISE) that takes your placed-and-routed design (.ncd) and tries to estimate the power based on actual (well, predicted) use.
Obviously, the second method will be more accurate, but you could get a ballpark for your power budget with the excel sheet before you have a complete design if you need to design your board.
Of course, the best method is to complete your design, run it on a prototyping board, and then measure the consumption. That rarely happens in practice, though, because the FPGA design and board bring-up usually happen in parallel.
(BTW, we're trying to start an SE site dedicated to FPGAs... consider supporting it... http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2)