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enter image description hereHi So far what all IC or micocontroller that I have used that use to have VDD = 5V & GND = 0V. Now I am working on an H-bridge circuit using IC driver IRS2110 for motor control.

What exactly we mean by these terms, and what are there role :

  1. High-side floating supply voltage ?
  2. High-side floating supply offset voltage ?
  3. What exactly the bootstrap capacitor is doing over here ?

Can someone help me to understand above concept.

Edit link :--
http://www.irf.com/product-info/datasheets/data/irs2110.pdf‎

In my half bridge circuit :---
VCC = 15V
Vdd = 3.3V

How will value of HO & LO will vary with HI & LI ?

HI pin 12 : 3.3
LI pin14 :0
Then I observed 8V at Gate

However when I kept HI:0V.
Then I observed 14V at gate. ( it should show low here ).

How will i have to trigger this IC to drive H-Bridge ?

Please suggest. enter image description here

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  • \$\begingroup\$ please provide a link to where you read this information and if a document state page number. \$\endgroup\$
    – Andy aka
    Oct 8, 2013 at 18:03
  • \$\begingroup\$ see electronics.stackexchange.com/questions/58849/… for a very good description of bootstrap bias function. \$\endgroup\$
    – gsills
    Oct 12, 2013 at 20:45

1 Answer 1

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The root of the problem to be solved by this circuit is that the Drain of the upper FET is not at a fixed voltage level (goes up & down), and you have to supply about 10V relative to its Drain at the Gate to open it.

What exactly the bootstrap capacitor is doing over here ?

It creates a voltage that is about (almost) VCC + VS. Since VS is sometimes almost equal to the highest power supply line within the circuit (up to 500V or 600V, according to the drawing in the data sheet), there would be no way to get a voltage ~10V higher than that without some kind of "magic". The magic works by charging a capacitor through a diode to about Vcc when Vs is at GND (lower FET is conducting), and then this capacitor can provide the neccessary voltage level needed to open the Gate of the upper FET, and keep the Gate at a higher voltage even when the upper FET opens and VS goes up.

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  • \$\begingroup\$ Thanks Laszlo .. one more thing what is an advantage to combine.. Vb and Vs with capacitor .. & .. Vcc & COM with capacitor .. ? \$\endgroup\$
    – user6363
    Oct 9, 2013 at 13:14
  • \$\begingroup\$ What to combine? I don't understand what you mean. \$\endgroup\$
    – Laszlo Valko
    Oct 9, 2013 at 22:37
  • \$\begingroup\$ Please see above attached image of the circuit.. \$\endgroup\$
    – user6363
    Oct 10, 2013 at 12:02
  • \$\begingroup\$ I can see the image, but still do not understand what you want to combine. \$\endgroup\$
    – Laszlo Valko
    Oct 10, 2013 at 15:33
  • \$\begingroup\$ I have re-edited the image above. Two point i need to clarify ... 1> Vb & Vs .. Vcc & COM are combined together by capacitor (i have circled them in red) 2> I have to change voltage across the load then how i have to drive HIN & LIN to achive this ? (means one pin HIN should be high other pin LIN should be low or apply PWM on these two pins) .. Please suggest on this. \$\endgroup\$
    – user6363
    Oct 10, 2013 at 17:27

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