I am adding two hex numbers and determining what bits in the condition code register. The numbers I am adding are 4D (base 16) and 66 (base 16). I converted both to their binary equivalents.

4D (base 16) = 0 1 0 0 1 1 0 1

66 (base 16) = 0 1 1 0 0 1 1 0

Once I added these I got 1 0 1 1 0 0 1 1. By looking at the MSB (bit 7), it is 1 which makes the number negative and the N bit is set to one. I was looking at my notes, when a number is negative, it is represented by its 2s complement.


1 0 1 1 0 0 1 1 = -(0 1 0 0 1 1 0 0 + 1) = - 0 1 0 0 1 1 0 1 = -4D (base 16) = -77 (base 10).

My professor said the V bit is set to 1 because of 2s complement overflow. For the 8 bit processor, the maximum value is +127 (base 10) and the minimum value is -128 (base 10). I thought 2s complement overflow occurred when the answer is outside these bounds. My answer is within these bounds so 2s complement overflow does not occur so I was wondering why the V bit is set to 1.

I put this into a hexadecimal calculator and it says the answer is B3 (base 16) which is what I got by just adding the numbers. This converts to 179 (base 10) which does go outside the bounds and the V bit would be set to 1.

So my professor did an extra step after I added the two numbers to display the negative equivalent. When should I determine if the V bit should be set, and what should the actual answer be, B3 or -4D?


2 Answers 2


A 2's complement overflow is indicated when the source values have the same sign but the resultant sign differs. In the case of your example, both source values have 0 as the MSB but the result has 1, therefore an overflow has occurred.

The sum is 0xB3, since the result itself is not modified by the status registers, only how you treat it after the fact.


For your processor, the 8 bits in a value can be interpreted in two ways:

  1. as an unsigned number, range 0 .. 255
  2. as a 2s-complement number, range -128 .. +127

(There are other ways an 8-bit value can be interpreted, for instance as an ASCII character, as a sign-magnitude encoded value, or as two BCD digits.)

It is up to the code to choose the correct interpretation, the ALU does not know. Hence the ALU in effect calculates BOTH results. The nice part is that the 8-bit result pattern is the same for unsigned and 2s-complement addition. (This is the main reason for the popularity of 2s-complement.)

But the confusing part is that the interpretation of the 8-bit results and especially of the status bits is different, depending on the interpretation.

  1. For unsigned addition, overflow occurs when there is a carry out of the 8'th bit. In your case this did not occur. Hence the Carry flag will be set to 'no carry'. In most chips this will be encoded as Carry = 0.
  2. For 2s-complement addition, (as Ignacio explained), an overflow occurs when the carry from the 7th bit to the 8th bit is different from the carry out of the 8th bit. This is encoded in the V bit.

The result of your addition can be summarized as X = 0xB3, C = 0, V = 1. How that should be interpreted depends on how the two input values should be interpreted. In the were unsigned values, the result is 0xB3 and no overflow occurred. If they were 2s-complement overflow occurred, and hence the 0xB3 has no meaning. (If no overflow occurred it would be a negative value.) If the two values had any other interpretation the result is probably meaningless.

Side note: a lot of processors have (had?) an additional status flag: the half-carry, which indicated a carry from bit 4 to bit 5. This was used when the two values each represented two BCD digits.


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