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I'm looking for a bullet-point list of a technique to experimentally determine a design's decoupling capability.

I have a design that I'm working on that seems to be susceptible to ESD events in the field. I can't change the PCB layout - but I'm thinking of doing a BOM change and replacing some decoupling capacitors with TVS diodes on the power rails.

I'd like to remove the capacitors and verify in the lab that the design still has sufficient decoupling.

The design has:

  • Altera Cyclone FPGA (32.768MHz)
  • Microchip PIC (Internal OSC - 8MHz)
  • Marvell Ethernet PHY (25MHz)

I have a 200MHz DSO 'scope in my lab. Do I just put a probe on a supply rail and trigger on large spikes, and if it never triggers after running through worst-case tests, it will be OK?

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  • \$\begingroup\$ cypress.com/?docID=31807 \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 9 '13 at 15:47
  • \$\begingroup\$ What are the symptoms when the design fails? I'm asking this because you could easily be missing a problem and wasting your time chasing down something that is not the cause. ESD generally finds the weakest point first and these are not usually the power rails. Regards your question, follow chip supplier guidelines for PCB layout and decoupling values. If the PCB layout is flawed decouplers will not fix this - bear that in mind. Getting your scope to see "spikes" is another waste of time - the scope has a very sensitive input and it will pick-up ESD discharges directly via the ether! \$\endgroup\$ – Andy aka Oct 9 '13 at 16:44
  • \$\begingroup\$ The failure: Power rails (+3V1, +1V2) are shorted to ground inside the FPGA and PHY. The question: I respectfully disagree - I don't think "follow this manufacturer app note" is a good way to verify the theory! I have this design, done by another engineer, and I cannot revisit the layout right now (we have 5k units in production). There are many variables to getting this "right" (cap ESR, trace inductance, package size inductance, etc) that are all unknowns to me. I hope you can understand that I would like to see in the lab how the PCB layout performs. \$\endgroup\$ – dext0rb Oct 9 '13 at 16:55
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    \$\begingroup\$ Does your company / industry have ESD tests you can perform in your lab? I suggest using those as a starting point and measuring your points of interest . I have used transient surge suppression tests in the past but only for compliance testing. \$\endgroup\$ – Spoon Oct 9 '13 at 18:37
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    \$\begingroup\$ What I'm trying to say is that if the PCB design is flawed then attempting to discover the decoupling effectivity is also a flawed idea. You may have 5000 in production but in my experience ESD affects inputs the most and they can cause the power supply problems you are seeing. Hoping that the problem can be solved by decoupling is fine but you have to establish that the PCB is not hindering the problem. Hire an ESD gun for a week - they cost about £150 in the UK - did that last month - get yourself a large piece of copper clad board for an earth plane and start zapping. \$\endgroup\$ – Andy aka Oct 9 '13 at 18:45
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Ok, ignoring your esd issue. Use the scope for sure and a high frequency signal generator capable of delivering up to 1GHz sourced from 50 ohms.

It probably would be better with a spectrum analyser the could handle up to 1GHz though.

Inject small signals onto the logic rails at various points and any weaknesses will be seen by the scope/analyser. 100mV p-p will do the job.

Also move the scope/analyser to different points while injecting. See if there are some frequencies that are more prone to generate bigger disturbances than others.

You might even be able to setup a pulse generator to do a similar job to the Sig gen. Stick with 100mV though to avoid damage.

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  • \$\begingroup\$ +1, but I'm wondering if you could expand a little. Why 1GHz? When you say inject 100mV P-P (square wave?) on "logic rails", you mean on the logic power supply rails, at various locations on the board. I should set the SigGen frequency to match the switching frequency of digital logic (or possibly sweep it thru all frequencies for thoroughness?) \$\endgroup\$ – dext0rb Oct 14 '13 at 17:52
  • \$\begingroup\$ Id start with sinewave from 1MHz ang go up to possibly 100MHz onto logic rails. Inject at any point and measure at same point to see if there are anomalies at some frequencies. Maybe even try squarewaves too. If there's a weakness it should show up. \$\endgroup\$ – Andy aka Oct 14 '13 at 18:02
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http://cp.literature.agilent.com/litweb/pdf/5989-5935EN.pdf

There is info here, and in Signal and Power Integrity Simplified by Eric Bogatin, that I may summarize at a later date. (because I am lazy right now...if someone else wants to clean it up before me, community wiki or something, go ahead.)

Basically though, you use a VNA to sweep the frequency and record the impedance. Make sure the impedance is under a target impedance you define over the frequencies of interest. Actually determining the target impedance is less-than-trivial(TM). There are some estimations/rules of thumb to help you mentioned in Bogatin and in Electromagnetic Compatibility Engineering by Henry Ott (Chapter 11)

Bottom line: When interested in decoupling capacitor effectiveness, you have to remember what capacitors are: frequency-dependent impedances. It makes sense, then, that you would want to measure the impedance of the Power Delivery Network (PDN), which in turn, will describe to you the ability of the PDN to meet transient current demands and keep the supply voltage within ripple spec.

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