I'm looking for a bullet-point list of a technique to experimentally determine a design's decoupling capability.
I have a design that I'm working on that seems to be susceptible to ESD events in the field. I can't change the PCB layout - but I'm thinking of doing a BOM change and replacing some decoupling capacitors with TVS diodes on the power rails.
I'd like to remove the capacitors and verify in the lab that the design still has sufficient decoupling.
The design has:
- Altera Cyclone FPGA (32.768MHz)
- Microchip PIC (Internal OSC - 8MHz)
- Marvell Ethernet PHY (25MHz)
I have a 200MHz DSO 'scope in my lab. Do I just put a probe on a supply rail and trigger on large spikes, and if it never triggers after running through worst-case tests, it will be OK?