I have implemented ram Verilog module. I made its instantiation and read the data from some address .After that I want to write the data to other address. looks that I don`t need to made the instantiation of the ram twice,since each ram defines different registers array.The question is how (should I?) reuse the same ram instance?
module ram(we,addr,data); input we; input[DATA_WIDTH - 1:0] addr, inout[DATA_WIDTH - 1:0] data; reg [DATA_WIDTH - 1:0] mem[0:ADDR_DEPTH - 1]; always @ ( posedge clk ) begin if(we) mem[addr] <= data; else data <= mem[addr]; end endmodule module top (add1,add2); wire [DATA_WIDTH - 1:0] w_data; ram i_ram1(1b'0,add1,w_data); ram i_ram2(1b'1,add2,w_data);//<- other mem array is used in this instance