I have implemented ram Verilog module. I made its instantiation and read the data from some address .After that I want to write the data to other address. looks that I dont need to made the instantiation of the ram twice,since each ram defines different registers array.The question is how (should I?) reuse the same ram instance?

module ram(we,addr,data);

input we;
inout[DATA_WIDTH - 1:0] data;

reg [DATA_WIDTH - 1:0] mem[0:ADDR_DEPTH - 1];
always @ ( posedge clk )
begin
if(we)
else
end
endmodule

wire [DATA_WIDTH - 1:0] w_data;
ram i_ram2(1b'1,add2,w_data);//<- other mem array is used in this instance

• You probably need to set data to Z when you are not driving the bus. If this is meant for FPGA synthesis, you want to have separate data-in and data-out busses. – The Photon Oct 10 '13 at 19:04

You'll need to use the clock to break up the write and read operations. Here is an example of a test bench that writes data to two addresses then reads them back.

wire [DATA_WIDTH-1:0] data = we ? wdata : {DATA_WIDTH{1'bz}}; // tri-state write output driver

initial begin
clk   = 1'b1;
data1 = 'h0F;
data2 = 'hF0;
we    = 1'b1;
wdata = data1;
@(posedge clk) #1;
wdata = data2;
@(posedge clk) #1;
we    = 1'b0;
@(posedge clk) #1;
if(data !== data1) $display("ERROR data:%h != data1:%h @ addr:%h", data,data1,addr); addr = addr2; @(posedge clk) #1; if(data !== data2)$display("ERROR data:%h != data2:%h @ addr:%h", data,data2,addr);
@(posedge clk) #1;
\$finish;
end


FLY if data is an inout, then you need a tri-state driver in your ram module:

assign data = we ? {DATA_WIDTH{1'bz}} : rdata; // tri-state read output driver
`

Full working example here: http://www.edaplayground.com/s/6/221

You have made two ram instances, given them two separate names, wired one of their write enable ports to zero and the other to 1. This will give you two rams, one of which is always being written to and one of which is always being read from.

Are you trying to run a simulation? What simulator are you using, we'll help you through it.