# Continuing execution after ISP in LPC81x series

I am uploading software via serial ISP in to an LPC81x series microcontroller. This is a Cortex-M0+ chip. After software upload, I would like to start the execution of the uploaded software without having to reset the CPU externally.

There is a "Go " command in the serial ISP and the "lpc21isp" software uses it as such: "G 0 T\r\n". However, this does not seem to work as it has several problems:

• The part of the program residing at address 0x00000000 is the interrupt vector table, not program code. Starting thumb mode execution at that address is just going to fault. However, I do not know what the "go" command really does.
• Somebody needs to set up the interrupt table pointer (VTOR), reset all the pin configurations and invoke the reset handler. This is quite different from starting execution at a certain address.
• The documentation says that using the "go" command on an address below 0x00000200 is not supported. In my case atleast the reset handler resides below that address.

I am open to any suggestions that would allow me to continue execution after ISP.

Just as extra information: the reason I wish to do this is that I do not have spare communication lines for reset or forcing ISP. I can, however, toggle the power to the chip. I would like the chip to unconditionally start in ISP mode, so I can update the software on every chip bootup if I wish.

I have the same problem. The ISP 'GO" command does not work for Cortex. In fact it can't work, because on a Cortex the initial SP is loaded from a particular address, not set by the code as for ARM chips.

My workaround is to reset the chip to force a reboot, by removing (and reapplying) the power. That's the only real way, because (at least on the chips I use) the 'reset' pin can be configured as GPIO.

• Unfortunately, triggering a reboot does not work for me, as I have very few inputs at my disposal and I need to reliable by able to get to the ISP, no matter what I do. Oct 11, 2013 at 6:25
• For the chips I use a power cycle + pulling down the BOOTMODE pin is the ONLY way to force a reliable entry to ISP. Note that I don't use the reset pin. Oct 11, 2013 at 6:35
• Yes, I am doing the same - except that I do not have enough inputs from the controlling side to control power, bootmode, tx and rx. That's why I need to have the bootmode pin always pulled down, and I would need to be able to continue on from the ISP. Oct 11, 2013 at 6:43
• Maybe you could have the ISP jump to a piece of code that explicitly loads the SP and then the PC. But I never tried that. Another 'cheat' would be to have a small microcontroller (PIC10F200?) that listens to the serial communication and can be instructed to releases BOOTMODE. Oct 11, 2013 at 10:07
• Just connect BOOTMODE to RX and send a BREAK or a slow 300 Baud 0x00 at the same time as Reset release. Oct 11, 2013 at 10:13

Using the Watchdog is not an option? The LPC81x features a watchdog which can be set/disabled and also contains a flag if the reset was triggered by a watchdog reset.

• I've tried using the watchdog, but any watchdog reset seems to bring me back to ISP as long as the ISP entry pin is held low. Jan 11, 2014 at 8:37
• Also if you read the Reset Register and determine that the reset was triggered through a watchdog? Jan 11, 2014 at 10:13

I have the same problem with the LPC 8xx in an application, where the only connection to the outside is RX and TX, power cycling and triggering the reset pin is not an option. I opened a support case at NXP, While I'm waiting for their answer, I found the following workaround.

1. Make sure you have a soft reset function in your code. E.g. NVIC_SystemReset
2. Link this function to a fixed location in flash memory on address 0x200 or above. Look in the documentation of your IDE/Linker how to do that.
3. After programming, execute the "Go" command. For 0x200 use "G 512 T".

This works fine for me, but I cannot understand why they haven't implemented a reset command in their bootloader.

Can you specifiy you own GO address in lpc21isp? If no, try using mxli, this works fine for me using the -j[address] option.

Also check out the "reinvoke ISP" command described in the IAP section for entering ISP mode from application.

I got an answer from NXP:

If you know the address of your startup code (from the linker map) you could use the GO command to start the user code. The way you do it, using the SystemReset function is even better, because it generates a real reset and initiates all register values to their defaults. There is no better way to start program execution after a firmware upgrade.

• I can do this.... and I can go to a specific address, and even do the "resume from interrupt table" magic that one of the LPC ISP tools can do (it uploads a small ARM snippet to execute). However, the problem here is that the processor is in the state it is in ISP, which is not the same as the after reset state - the UART is configured etc. In addition, maybe I'm missing something, but wouldn't I need to change some other memory remaps or something after this or how do I make sure all interrupts land in my code instead of the ROM interrupt table? Jan 11, 2014 at 8:40
• I've also discussed this with NXP, and didn't get a fully working solution, maybe your luck is better. Also, the "ramloader" firmware could also be a starting point in solving this: lpcware.com/content/forum/entire-ram-execution-ramloader Jan 11, 2014 at 8:43
• But when you execute a softreset, the processor state should be the same as after powerup reset, no? The soft reset should also reload your IRQ table from flash. Jan 11, 2014 at 12:56
• It does not, because the ISP entry pin has been sampled low, so the softreset reloads IRQ table from ROM, just like the powerup reset. Jan 12, 2014 at 23:06
• Yes, but if the application is valid, then the ROM should load it from the flash? I simply disable the sampling of the pin in the CPR and added a command to reinvoke ISP in my application. Is this an option for you? Jan 13, 2014 at 13:56