Im trying to learn a bit about the techniques to create an ASIC. I found that the NRE-Costs are the biggest cost part which means the creationg of the masks and you get a minimum number of ASICs back.

Shuttle Services seems to be cheaper which means that more ASIC-Designs are done at the same time. So the part of the costs one has to pay is smaller. But the resulting ASICs are less too.

But what about the masks resulting from that. Are they have a disadvantage against a dedicated run? I mean will producing more ASICs be more expensive since the mask only is for, maybe, 1 ASIC instead a full mask for many of the same ASICs?

In fact my question is if the costs one is saving by using shuttle services is firing back later when producing more ASICs.

If someone knows... whats the cheapest way to get a most optimized (custom) ASIC that has the potential to create more of the same ASICs for cheap later. Maybe 28nm or even lower...

  • \$\begingroup\$ This question appears to be off-topic because it is not about electronic design. \$\endgroup\$ – Leon Heller Oct 12 '13 at 17:49
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    \$\begingroup\$ @LeonHeller it's hard to imagine how this is NOT about design. Deciding how something is produced/manufactured and how much it costs is key to understanding how to design it. Does the fab supply the libraries I need? and a shuttle service or will I have to go to an FPGA or another fab? In fact if you read my answer you'll see that if you are forced to use a shuttle one might actually change your layout to ensure that it can yield some chips. \$\endgroup\$ – placeholder Oct 12 '13 at 18:50

Actually the biggest cost is the design itself, then followed by the fab NRE (Fracture costs and mask making).

The biggest risk that you have from a using a Shuttle/MPW is that you often are on the same mask set as someone who is experimenting or who may not understand areal density rules. The worst is when you have some grad student playing around with inductors and ruining the plananarization of adjacent chips. If you are doing something more advanced or needing better matching then you should forget it. Most P&R tools should be OK for routing density, it's the odd wild card that you share the mask with that can screw you up.

Do keep in mind that with an ASIC fabless model, "proof" of a good wafer run is the from the process monitors that the fab measures. NOT your design yielding, that is your responsibility.

The next step up, before a full production mask set is the placement of multiple layers on one mask to reduce the mask making costs. This mask this then used (with blading) and may reduce mask costs to 1/4 or 1/3 (fracture costs stay the same). But the fab will not go to production with this as it slows things down. Not all fabs offer this, and different fabs use different terms for this service.

  • \$\begingroup\$ What are "fracture costs"? I couldn't find a definition online. \$\endgroup\$ – Randomblue Sep 9 '18 at 19:57

Yes, shuttle service puts many projects on one wafer, thereby dividing the NRE among the projects. If you want a proper production run (thousands), then you should get a proper mask set made.

Really you have to decide how many you're going to sell before you start the project, so you can choose accordingly.

28nm is never going to be cheap. It also has its own difficulties; as a startup you should probably be targeting more like 90nm.


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