# minimum clock cycles needed?

The instruction call Rn,sub is a two word instruction.Assuming that PC is incremented during the fetch cycle of the first word of the instruction,its resister transfer operation is

Rn<=PC+1;
PC<=M[PC];


Someone please help me to calculate minimum clock cycles needed during the execution cycle of the instruction.I am student of computer science and not very good in microprocessor ,please explain how to count minimum clock cycles?

Should it not be 5 in 8085.

2. Cycle to increment PC (PC+1)
3. Transferring it to Rn from accumulator.
4. 2 cycles for memory read operation.

• It'd be worth mentioning the type of architecture. The usual way isn't really to calculate it, you'd normally look it up in the architecture guide for the particular processor to find it. If it's an assignment of some sort maybe you have a block diagram of the CPU you could add? – PeterJ Oct 13 '13 at 4:31
• minimum is asked here so what will be the minimum with any possible architecture? And also what will be if it is just 8085? – user1766481 Oct 13 '13 at 4:35
• If you allow arbitrary architectures, the answer of minimum clock cycles for any operation is always 1. This is assuming an architecture that has a assembly opcode that directly corresponds to the two lines of code you present, and can execute that operation in a single-cycle, is 1 clock cycle. Now, for real-world architectures, the answer is likely very different. – Connor Wolf Oct 13 '13 at 9:45

To answer such a question a lot more context must be given and assumptions must be made explicit. Just a few issues:

1) The call-method you describe here is typical for ARM/Cortex and some less known architectures. An 8085 uses the more common stack based method.

2) Most architectures have dedicated hardware and data paths for incrementing the PC, so the ALU does not need to be involved, and it can be done in parallel with another operation.

3) An 8085 is an 8-bit architecture with a 16-bit address, hence getting an address from memory involves two memory accesses (with accompanying PC increments).

4) You seem to assume that a memory access takes 2 internal cycles worth of time. IIRC it was 1 for an 8085 (but I might be wrong), and it is often many many more for modern processors.

5) In step 3) you mention an accumulator, you probably mean the ALU result register, which on most register-based architectures is not a programmer-visible register.

6) If storing the result in Rn takes a cycle, it seems reasonable to assume that storing the destination address in the PC also takes a cycle.