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I would like to know one thing that say if you know Processor word length(TMS320VC5510 DSP) it accumulator and guard bits can you make a guess about filter characteristics to be used for this architecture. just to be more precise lets put following values as an example.

The processor word length is 16 bits and it has a 40 bit accumulator with 8 guard bits So what kind of filters (Filter Characteristics ) you can use for the above mentioned architecture and how you predicted i mean by analyzing what?. what i can do so far is that may be a loww pass filter with range around [-3,3) can be used.

Regards

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    \$\begingroup\$ word length isn't related to filter characteristic at all if I understand your question correctly. Have you looked up FIR and IIR filters? \$\endgroup\$
    – Andy aka
    Oct 13, 2013 at 10:28

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No, the architecture has nothing to do with the kind of filters that can be implemented. Architecture will give you a certain speed and resolution for any particular filter implementation.

In your case you are apparently thinking of a convolution filter. The coefficient are 16 bits, and you say the accumulator is 40 bits wide. Presumably the data samples in memory are also 16 bits wide. This means a 16 x 16 bit multiply will be performed per data point. This produces up to a 32 bit number. With a 40 bit accumulator you know that you can add up at least 256 such numbers. Depending on how the guard bits work, you may actually be able to sum 65536 data points before a real overflow. In that case there is probably a instruction to find the highest significant bit of the result so that a shift can be performed to ultimately keep the top bits. In some cases the maximum range of the result will be bounded due to inherent properties of the filter and the data stream being filtered.

In this example, there is some quantization noise on each coeficient, each data sample, a limit on the number of significant result bits, and some maximum number of multiply-accumulates that can be performed each data sample period. These are all parameters that are a function of the architecture. Note that the coeficient value, and therefore the response of the filter, has nothing to do with the architecture.

You also don't have to use the DSP hardware directly. You could, for example, do your own wide multiply-accumulate code that keeps more bits per value and has a wider result word. The drawback is that since this would be significantly slower, the number of coeficients would be much less. Everything is a tradeoff.

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  • \$\begingroup\$ Thank you so much for this thorough explanation. i am really humbled by your response \$\endgroup\$
    – Loraloper
    Oct 13, 2013 at 14:26
  • \$\begingroup\$ A better approach if one wants a sum that's wider than the DSP's accumulator can support directly is to subdivide the operation into chunks that will fit in the DSP's accumulator. Doing a 1024-point multiply-accumulate as four 256-point ones, for example, is apt to be much faster than doing 1024 individual multiply and add operations. Even if one wanted to multiply-accumulate 16-bit data points by 32-bit coefficients and hardware could only handle 16x16 multiplies, storing each 32-bit coefficient as a separate high- and low- half and... \$\endgroup\$
    – supercat
    Oct 13, 2013 at 18:53
  • \$\begingroup\$ ...performing separate MAC operations for (dataPoints * highCoefficients) and (dataPoints * lowCoefficientss), scaling the results, and adding them together, would be faster than doing things point-by-point. \$\endgroup\$
    – supercat
    Oct 13, 2013 at 18:55
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A limited word length in a DSP causes excess quantization (i.e., a large quantization step size) of data samples, raising the noise floor, and of filter coefficients, which can make the actual response of the filter deviate from its theoretical value. The latter effect is most visible in the area of reduced stop-band attenuation.

Is this the sort of thing you're looking for?

For example, in an FIR filter, the coefficients also define the filter's impulse response. Also, for any filter, the Fourier transform of its impulse response is its frequency response.

It is an interesting exercise to draw a curve representing the desired frequency response and take its inverse Fourier transform to get the impulse response. In any real implementation, you're going to have to select a finite number of coefficients, and you're going to have to apply a "window" function to those coefficients in order to limit the effects of the truncation on the impulse response.

Take the Fourier transform of these coefficients and see how the resulting frequency response deviates from the ideal response you started with.

Now, quantize those coefficients to the precision they'll actually have on the DSP. Take another Fourier transform and see how this has further modified the frequency response.

In some cases, the effects can be dramatic. Doing this a few times can give you a good sense of the level of filter performance you can expect for various values of filter length and word width.

To address the overflow issues that Olin is alluding to, you would normally scale the coefficients during the design phase so that the maximum gain in the filter's passband is unity. However, this can create additional quantization errors in the coefficients, causing the smaller ones to disappear altogether. If the hardware of the DSP includes, say, an 8-bit overflow field on the MAC accumulator, you might set the coefficient gain to 256 instead, and then shift the output samples right by 8 bits to get an overall gain of unity.

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