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I am working on a circuit that has two devices that are each supposed to have decoupling capacitors. In this case however, the devices are right next to each other, and their power supply pins are right next to each other (let's say, 1mm apart). Can a single decoupling capacitor be used for both devices?

Similarly, I have a LDO regulator for the power supply which requires a 1uF capacitor on its output for stability, can that be the same capacitor as the decoupling capacitor for both devices as well? I can move the LDO right next to the power pins of both devices.

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General-purpose decoupling caps are rarely engineered to precise tolerances. In most cases, there's a huge range of values (generally many orders of magnitude) that will work, although those near the extremes aren't as good as those nearer the middle. For example, a 3.3 volt chip might malfunction if the voltage dips by 0.5 volts or more, but work correctly if it dips by 0.49 volts or less; from the chip's perspective, a bypass cap that allows VDD to briefly dip 0.4 volts would be adequate, but any "high" outputs would dip by 0.4 volts any time VDD does. That might not make attached devices malfunction, but could increase the amount of radiated interference or make the device more susceptible to radiated interference that arrives just at the moment of a dip. Since such dips on VDD are ugly, and it's often difficult to guarantee when they will or will not be problematic, designers generally try to use sufficient bypass caps to keep VDD dips below 100mv or so.

Consequently, if one were to place a bunch of chips on their sides radially around a bypass cap, one could probably achieve acceptable electrical bypassing using one cap for a dozen or so chips (figuring that every chip would be within 0.1" or so of the cap). From a practical perspective, however, trying to have a dozen chips that close to a single bypass cap would be a manufacturing nightmare. What is required is not that one have a bypass cap for every chip, but rather that each chip power input have a very short direct connection to a bypass cap; achieving that is generally easiest if each chip has its own bypass cap, but if the layout allows two chips to have good bypass connections to a single cap, and both chips are comparably sensitive to VDD noise, sharing a bypass cap is generally just fine.

Incidentally, another thing to consider with bypass caps is the consequence of not having them: if a chip doesn't have a bypass cap, one should assume that its internal state will be scrambled and combinatorial outputs may randomly glitched briefly when any input changes. If the a chip has no internal state that one cares about, and is used in such a fashion that one wouldn't care if the outputs glitched in response to input changes (e.g. its inputs all change synchronously with a common clock signal, and the outputs won't be sampled until some time later), one may be able to omit that chip's bypassing altogether. Proper bypassing would likely reduce electromagnetic interference, but from an operational standpoint it wouldn't affect anything.

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  1. Yes it can. No problem at all. It is a common practice, group of near placed devices to have one decoupling capacitor(s).

  2. Yes, the output capacitor of the LDO can be a decoupling capacitor for these devices, again if it is very close to them. Consider increasing its capacitance according with decoupling needs.

In all cases provide short and thick tracks for the power. The low inductance is essential here.

Don't forget that if you have electrolyte capacitor there, it have to be coupled with a low inductance ceramic capacitor.

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If the decoupling capacitor specified for chip A is the same value as the decoupling capacitor specified for chip B then this should be OK but be aware that if different coupling capacitors are specified you shouldn't take the risk.

A 10nF de-coupler for chip A might have a series resonant frequency of 30MHz whereas a 100nF de-coupler for chip B might have a series resonant frequency of 5MHz. They will both have different ESR (effective series resistances) and choosing the higher value cap may cause noise problems on the chip that specified the lower value cap. Choosing the lower value cap may give problem to the chip that wanted the higher value "bulky" cap.

If both chips are specified as requiring a 1uF de-coupler then there is likely no problem in them sharing the 1uf with the LDO but, if the regulator was a switching type then it's not worth the risk.

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  • \$\begingroup\$ I would also make sure the cap value is high enough to eliminate transients that may occur of both ICs switch at the same time. And I agree, too risky to share the cap with the regulator unless it's linear. \$\endgroup\$ – scld Oct 14 '13 at 12:54

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