# Why do we assume VGS<Vth and Vds>0 for a mosfet in cuttoff and Vce>0 for a BJT in cutoff?

The devices below are both n polarity devices, the BJT is a NPN and the MOSFET is a NMOS.

1. For the BJT in cut-off, why do we have to assume $V_{ce}>0$?

2. For the MOSFET in cut-off, why do we have to assume $V_{GS}<V_{th}$ and $V_{DS} > 0$?

Where VGS is the gate-source voltage and Vth is the threshold voltage. simulate this circuit – Schematic created using CircuitLab

• V_th is the threshold voltage. – Dave Tweed Oct 16 '13 at 17:25
• They can't BOTH be NPN devices. One is NPN the other is a NMOS. – placeholder Oct 16 '13 at 17:39

A simple model for you is to think of the term cutoff to mean that the device is "cut off" or not operating or not controlling that pin (the collector in the NPN or the Drain in the NMOS). In both of those cases it just means that the pin can take any value that it wants or is imposed upon it by other circuitry. So it really means that $V_{DS}>= 0$ and $V_{CE} >= 0$ i.e. any value it wants.

For the BJT in cut-off, why do we have to assume $V_{ce}>0$?

If the NPN is in cut-off (as defined by very low base current $I_{b}$), its C-E behaves as an open circuit, so its voltage will be determined by whatever it is connected to, be it negative or positive (so $V_{ce}>0$ is not required).

However, if the external circuitry tries to make $V_{ce}$ negative, $V_{bc}$ may become positively biased and $I_{b}$ will increase by flowing to the collector. In this case the BJT will no longer be in cut-off, and the behavior will be as if the C-E terminals were reversed, but with much lower performance, breakdown limits, and overall specs.

The following graph should help: (source)

Also, see BJT in Reverse Active Mode of Operation for a related discussion.

For the MOSFET in cut-off, why do we have to assume $V_{GS}<V_{th}$ and $V_{DS} > 0$?

$V_{GS}<V_{th}$ pretty much defines the cut-off region (very little current will flow), and $V_{DS} > 0$ is required because if it is sufficiently negative, current will flow via the body diode from source to drain. So the condition should really be $V_{DS} > -Vdiode$. 